{"id":4027662,"url":"https://alion.io/job/ciena-corporation-lead-analog-layout-engineer","title":"Lead Analog Layout Engineer","company":{"id":1996,"name":"Ciena Corporation","domain":"ciena.com","url":"https://alion.io/company/ciena","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":78,"open_postings":32,"ghost_share":0,"stale_share":0.844,"repost_share":0.031,"time_to_fill_p50_days":30,"computed_at":"2026-11-11T05:49:22Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"remote","remote_scope":"stated_countries","remote_scope_basis":"board_field","remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Ottawa, Canada","Canada"],"countries":["CA"],"hiring_countries":["CA"],"hiring_countries_total":1,"salary":null,"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Cadence Virtuoso","optional":false},{"name":"Siemens Calibre","optional":false},{"name":"Ansys Totem","optional":true}],"status":"live","first_seen_at":"2026-11-10T17:31:00Z","employer_posted_date":"2026-11-10","last_verified_at":"2026-11-11T15:57:24Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being-on and off the job. Connect with a career that matters.\nThe Lead Analog Layout Engineer shapes the high-speed silicon behind Ciena's WaveLogic coherent optical communications products by owning critical analog and mixed-signal layouts from feasibility through tapeout. This hands-on individual-contributor technical leadership role sets layout direction, coordinates delivery with circuit designers and layout contributors, and advances implementation in advanced CMOS technologies. The role builds on more than 30 years of team innovation in high-speed ADC and DAC macros for coherent optical transmission while extending capabilities into high-speed SerDes.\nHow you will make an impact:\nOwn assigned layout projects from feasibility and floorplanning through implementation, physical verification, integration, and tapeout readiness.\nDefine project scope, implementation plans, effort estimates, milestones, and review checkpoints with circuit designers and engineering leads; coordinate contributors, track dependencies, and resolve implementation bottlenecks.\nLead layout reviews and quality checks with the layout team and circuit designers.\nPartner with circuit designers to establish implementation constraints and evaluate performance, area, device matching, parasitics, isolation, and reliability tradeoffs.\nDevelop layout strategies for performance-critical circuits and high-speed signal paths; review extracted parasitics and implement targeted improvements.\nDrive physical-verification and reliability closure, including DRC, LVS, ERC, antenna, BUMP, EM/IR, and PERC checks.\nMentor junior engineers through hands-on problem-solving and design feedback; partner with CAD and AI/ML engineers on environment setup, tool evaluation, automation, reusable layout structures, RFIC and analog layout generation, PCell development, and design space exploration; communicate progress, risks, and corrective actions against milestones.\nThe must haves:\nEducation: Bachelor's degree or higher in Electrical Engineering, or a related field.\n Experience: 5+ years of custom analog or mixed-signal IC layout experience, including ownership of complex layouts through successful tapeouts, independent technical decision-making, project delivery, guidance of layout contributors, and hands-on implementation.\nApplication of layout expertise in one or more circuit families, such as ADCs, DACs, SerDes, PLLs, high-speed amplifiers, or precision analog circuits.\nUtilization of Cadence Virtuoso and Siemens Calibre, or comparable custom-layout and physical-verification tools.\nApplication of device matching, parasitic resistance and capacitance, coupling, high-frequency routing, shielding, ESD-aware layout, electromigration, and IR drop.\nApplication of deep-submicron CMOS processes, foundry design rules, device isolation, and layout-dependent effects to performance and reliability challenges.\nCollaboration with circuit designers, analytical problem-solving, attention to layout quality, and communication of technical tradeoffs.\nNice to haves:\nPractical experience with FinFET layout and advanced-node implementation.\nExperience in high-speed SerDes or data converters.\nAnsys Totem or comparable EM/IR tools and PERC-based ESD and reliability debugging.\nDeep knowledge of noise isolation and shielding.\nPCell development and layout automation skills.\nExperience using AI-assisted coding tools to develop and validate layout-flow scripts, automation, and engineering utilities.\nPay Range:\nThe annual pay range for this position in Canada is C$141,700 - C$226,000.\nPay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.\nNon-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.\nAt Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.\nCiena is an Equal Opportunity Employer, including disability and protected veteran status.\nIf contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.","description_format":"text","description_chars":5310,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Parental leave"],"hiring_locations":[{"name":"Canada","iso":"CA","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Telecom Infrastructure","Optical Communications"],"lifecycle":[{"event":"open","at":"2026-11-10T17:31:00Z"}],"visa":[{"country":"CA","licensed_sponsor":true,"adverts_offering_sponsorship_24m":0,"sanctioned_now":false,"evidence":"Positions approved through LMIA in 12 months: 4","filings_12m":4,"filings_prev_12m":3,"green_card_filings_12m":null,"median_offered_wage_usd":null,"route":"Global Talent Stream; High Wage","cap_exempt":false,"checked_at":"2026-11-11T07:38:50+00:00","sources":["ESDC: employers issued a positive LMIA"],"filings_for_role_12m":1}],"liveness":{"score":60,"band":"ok","label":"Likely open","p_open":1,"p_active":0.602,"p_room":1,"age_days":0,"expected_fill_days":30,"reasons":["conf:0","stale_co","win:early","comp:brand"],"computed_at":"2026-11-11T05:49:22Z"},"pay":null,"html_url":"https://alion.io/job/ciena-corporation-lead-analog-layout-engineer","json_url":"https://alion.io/job/ciena-corporation-lead-analog-layout-engineer.json","meta":{"generated_at":"2026-11-11T19:17:44Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":37242,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-12T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":1996},"rest":"https://alion.io/mcp/rest/get_company?id=1996"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fciena-corporation-lead-analog-layout-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":2,"usd":0.2},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fciena-corporation-lead-analog-layout-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fciena-corporation-lead-analog-layout-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/ciena-corporation-lead-analog-layout-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fciena-corporation-lead-analog-layout-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":4027662}},{"tool":"search_jobs","arguments":{"company":"ciena.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":4027662},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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