{"id":2227850,"url":"https://alion.io/job/ciena-principal-serdes-systemdsp-design-engineer","title":"Principal SerDes System/DSP Design Engineer","company":{"id":1996,"name":"Ciena Corporation","domain":"ciena.com","url":"https://alion.io/company/ciena","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":80,"open_postings":25,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":10,"computed_at":"2026-10-14T06:34:16Z"}},"role":"DevOps","role_family":"DevOps","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Ottawa, Canada","Braunschweig, Germany","Canada"],"countries":["CA","DE"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":126100,"max":201500,"currency":"CAD","period":"year","gross":null,"usd_annual":141378},"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"C++","optional":false},{"name":"MATLAB","optional":false},{"name":"Python","optional":false}],"status":"live","first_seen_at":"2026-03-27T00:00:00Z","employer_posted_date":"2026-03-27","last_verified_at":"2026-10-14T13:34:34Z","board_verified":true,"closed_at":null,"days_open":201,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":201},"description":"As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity-driving our business priorities alongside meaningful social, community, and societal impact.\nWe’re building the next generation of 448G electrical SerDes and pioneering optical IMDD systems to power tomorrow’s networks. Our engineering team lives at the intersection of high-performance DSP design, system modeling, and optical innovation.\nHow You Will Contribue:\nWe are seeking a highly skilled Senior SerDes System/DSP Design Engineer to join our advanced engineering team . In this role, you will lead the architecture, design, and validation of high-speed serial transceivers across electrical and optical domains. You will leverage your expertise in systems engineering, control theory, DSP algorithms, and modeling to develop cutting-edge serial electrical/optical-IMDD transceiver solutions.\nThis position offers the opportunity to work on industry-leading designs at the intersection of electrical SerDes technology and advanced optical communications, driving innovations that enable next-generation high-capacity networks.\nLead the design and development of electrical SerDes DSP architectures for high-speed data communication systems.\nPerform system-level evaluation, modeling, and performance analysis of SerDes transceiver solutions including impairments and mitigation techniques.\nDevelop algorithms and architectures for adaptive equalization, maximum likelihood sequence detection (MLSD), and timing recovery algorithms.\nIntegrate control theory and advanced DSP designs into feasible hardware implementations.\nCollaborate with cross-functional teams (analog design, ASIC design, electro-optical hardware, firmware) to optimize SerDes performance in end-to-end systems.\nConduct design trade-offs to meet stringent performance, power, and area targets.\nAnalyze channel models, analog circuits impairments (DAC, ADC, AFE, …) and system constraints to determine system level margin and FEC (forward error correction) performance and optimize system margin.\nProvide system level specifications for different sub-blocks of SerDes transceivers such as DAC, ADC, AFE, PLL.\nEvaluate and model IMDD optical links and formulate strategies to enhance system robustness.\nDocument design specifications, system performance results, and contribute to IP generation and innovation roadmaps.\nThe Must Haves\nAdvanced expertise in electrical SerDes DSP design and implementation.\nProven experience in SerDes system-level evaluation, modeling, and simulation.\nStrong proficiency in control theory and digital signal processing (DSP) applied to high-speed communication systems.\nFamiliarity with optical IMDD (Intensity Modulation Direct Detection) systems.\nDeep understanding of adaptive equalization techniques for high-speed links.\nProficiency with maximum likelihood sequence detection (MLSD) approaches.\nExpertise in timing recovery schemes in high-speed serial links.\nPractical knowledge of FEC performance modeling and system-level performance optimization.\nExperience with MATLAB, Python, or C/C++ for algorithm design and simulation.\nStrong problem-solving skills and ability to work across hardware/software boundaries.\nPh.D. in Electrical Engineering with background in digital communications and signal processing.\n8+ years of experience in high-speed serial link or communication system design.\nNice to Haves:\nKnowledge of industry standards such as PCIe, IEEE, Ethernet, or OIF standards for optical communication.\nHands-on experience with lab bring-up, characterization, and debugging of SerDes links.\nPay Range:\nThe annual salary range is $126,100 - $201,500 CAD.\nPay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.\nNon-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.\nAt Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.\nCiena is an Equal Opportunity Employer, including disability and protected veteran status.\nIf contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.","description_format":"text","description_chars":5284,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"phd","optional":false},"security_clearance":false,"languages":[]},"benefits":["Flexible schedule","Parental leave"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Telecom Infrastructure","Optical Communications"],"lifecycle":[{"event":"open","at":"2026-10-10T16:58:59Z"}],"visa":[{"country":"CA","licensed_sponsor":true,"evidence":"Positions approved through LMIA in 12 months: 5","filings_12m":5,"filings_prev_12m":2,"green_card_filings_12m":null,"median_offered_wage_usd":null,"route":"Global Talent Stream; High Wage","cap_exempt":false,"checked_at":"2026-10-03T21:10:52+00:00","sources":["ESDC: employers issued a positive LMIA"],"filings_for_role_12m":2}],"liveness":{"score":5,"band":"cold","label":"Long shot","p_open":1,"p_active":0.178,"p_room":0.28,"age_days":201,"expected_fill_days":10,"reasons":["conf:11","stale_co","win:tail","crowd:brand"],"computed_at":"2026-10-14T06:34:16Z"},"pay":{"stated_usd_annual":141378,"is_top_pay":false},"html_url":"https://alion.io/job/ciena-principal-serdes-systemdsp-design-engineer","json_url":"https://alion.io/job/ciena-principal-serdes-systemdsp-design-engineer.json","meta":{"generated_at":"2026-10-14T17:24:09Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":22300,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-15T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":1996},"rest":"https://alion.io/mcp/rest/get_company?id=1996"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fciena-principal-serdes-systemdsp-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fciena-principal-serdes-systemdsp-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fciena-principal-serdes-systemdsp-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/ciena-principal-serdes-systemdsp-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fciena-principal-serdes-systemdsp-design-engineer"}]}