{"id":2227815,"url":"https://alion.io/job/ciena-senior-asic-design-engineer-client-ip","title":"Senior ASIC Design Engineer - Client IP","company":{"id":1996,"name":"Ciena Corporation","domain":"ciena.com","url":"https://alion.io/company/ciena","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":80,"open_postings":24,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":10,"computed_at":"2026-10-13T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Ottawa, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":73000,"max_usd":130000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":60},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Jira","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false}],"status":"live","first_seen_at":"2026-08-06T00:00:00Z","employer_posted_date":"2026-08-06","last_verified_at":"2026-10-12T19:27:19Z","board_verified":true,"closed_at":null,"days_open":68,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":68},"description":"As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity-driving our business priorities alongside meaningful social, community, and societal impact.\nHow You Will Contribute:\nThe Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions and are one of the main contributors to Ciena's success in the telecommunications industry. To further strengthen our team, we are looking for an enthusiastic digital design engineer who will be involved in the design of these products, working within a team of digital design engineers, verification engineers and architects.\nYour role as a senior digital design engineer will be to propose innovative solutions, in order to design power and area optimized functional blocks for the Wavelogic family of products.\nAs a senior digital design engineer, you are expected to read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects\nYou will produce an implementation specification document and have it reviewed by your team, architects, analog designers if applicable\nYou are accountable for the creation and integration of new and existing RTL code, algorithms and functions\nYou are held responsible for designer testing of your code as well as debugging of your code during simulation and regression verification\nYou will assist the verification team in determining coverage and provide design assertions and waivers as needed\nYou are held responsible for crafting timing constraints for your code, and will participate in synthesis log reviews, constraint reviews, timing report analysis, layout and backend reviews\nYou will be involved in lab validation of the product and its prototype if applicable\nYou are expected to report on status updates on a regular basis\nThe Must Haves:\nElectrical or computer engineering, or other applicable scientific degree at the BEng/BSc or MEng/MSc level\nExperience: 5+ years using System Verilog for design\nExperience: 5+ y ears running digital design synthesis, STA, timing closure and asynchronous clock crossings\nA highly motivated self-starter, able to work independently, while being a team player\nAbility to methodically solve complex technical problems\nExcellent organization, written and oral (English) communication skills\nFamiliarity with digital (including formal) verification methods\nGood understanding of timing/power/area analysis and trade-offs\nAssets:\nExperience with digital silicon design backend process\nExperience with digital design for low power\nExperience with standards and protocols such as OTN/FlexO/B100G, Ethernet (100GE+)\nExperience with usingGIT for source code management and revision tracking\nExperience with using Jira for schedule planning, assignment tracking and bug reporting\nFamiliarity with programming languages such as Python, Make, bash.\nThe annual pay range for this position is $109,000 - $174,000 CAD.\nPay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.\nNon-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.\nAt Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.\nCiena is an Equal Opportunity Employer, including disability and protected veteran status.\nIf contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.","description_format":"text","description_chars":4609,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[{"language":"English","level":"Upper-Intermediate (B2)","optional":false}]},"benefits":["Flexible schedule","Parental leave"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Telecom Infrastructure","Optical Communications"],"lifecycle":[{"event":"open","at":"2026-10-10T16:58:59Z"}],"visa":[{"country":"CA","licensed_sponsor":true,"evidence":"Positions approved through LMIA in 12 months: 5","filings_12m":5,"filings_prev_12m":2,"green_card_filings_12m":null,"median_offered_wage_usd":null,"route":"Global Talent Stream; High Wage","cap_exempt":false,"checked_at":"2026-10-03T21:10:52+00:00","sources":["ESDC: employers issued a positive LMIA"],"filings_for_role_12m":2}],"liveness":{"score":6,"band":"cold","label":"Long shot","p_open":1,"p_active":0.222,"p_room":0.28,"age_days":68,"expected_fill_days":10,"reasons":["conf:10","stale_co","win:tail","crowd:brand"],"computed_at":"2026-10-13T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/ciena-senior-asic-design-engineer-client-ip","json_url":"https://alion.io/job/ciena-senior-asic-design-engineer-client-ip.json","meta":{"generated_at":"2026-10-13T07:18:34Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":10719,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-14T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":1996},"rest":"https://alion.io/mcp/rest/get_company?id=1996"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fciena-senior-asic-design-engineer-client-ip"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fciena-senior-asic-design-engineer-client-ip"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fciena-senior-asic-design-engineer-client-ip"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/ciena-senior-asic-design-engineer-client-ip\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fciena-senior-asic-design-engineer-client-ip"}]}