{"id":3455340,"url":"https://alion.io/job/ciklum-expert-logic-design-engineer","title":"Expert Logic Design Engineer","company":{"id":181259,"name":"Ciklum","domain":"ciklum.com","url":"https://alion.io/company/ciklum","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Oracle","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"remote","remote_scope":"stated_countries","remote_scope_basis":"inferred_payroll_markers","remote_working_hours":null,"hiring_geo_confidence":"inferred","locations":[],"countries":[],"hiring_countries":["CZ"],"hiring_countries_total":1,"salary":null,"salary_estimate":{"min_usd":111000,"max_usd":222000,"period":"year","method":"global_role_seniority_cell","sample_n":1936},"experience_years_min":6,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"Python","optional":true},{"name":"Synopsys VCS","optional":true},{"name":"Xilinx Vivado","optional":true}],"status":"live","first_seen_at":"2026-10-27T16:12:52Z","employer_posted_date":"2026-10-27","last_verified_at":"2026-11-01T03:49:41Z","board_verified":true,"closed_at":null,"days_open":4,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":4},"description":"Ciklum is looking for an Expert Logic Design Engineer to join our team full-time in the Czech Republic.\nWe are a custom product engineering company that supports both multinational organizations and scaling startups to solve their most complex business challenges. With a global team of over 4,000 highly skilled developers, consultants, analysts and product owners, we engineer technology that redefines industries and shapes the way people live.\nAbout the role:\nWe are looking for an Expert Logic Design Engineer to take a leading technical role in the architecture, design, and optimization of next-generation FPGA and ASIC-based control platforms.\nThis position involves solving challenging digital design problems with extremely demanding timing, latency, and performance requirements. You will work closely with system architects, verification engineers, software developers, and hardware specialists, driving technical decisions and contributing to the development of proprietary digital IP.\nOur client is an innovative technology company developing advanced control and measurement systems for quantum computing. Its hardware and software platforms enable precise, real-time control of complex quantum systems, supporting the evolution of quantum computing from individual qubits to large-scale architectures.\nResponsibilities:\nLead the architecture, microarchitecture, and RTL implementation of complex, high-performance FPGA/ASIC digital subsystems\nDesign and optimize highly configurable, ultra-low-latency digital logic using SystemVerilog\nDrive end-to-end digital IP development, from system requirements and architectural trade-offs to RTL implementation and integration\nMake architectural decisions to optimize timing performance, latency, resource utilization, scalability, and power efficiency\nAddress complex timing closure, clock-domain crossing, synchronization, and critical-path optimization challenges\nDevelop advanced digital processing and control architectures, including signal processing pipelines, waveform generation, and deterministic real-time control\nDefine hardware-software interfaces and collaborate with software and system architecture teams to ensure efficient system integration\nWork closely with verification engineers to define verification strategies and ensure robust functional coverage\nReview RTL designs, identify architectural and implementation risks, and provide technical guidance to other engineers\nContribute to the evolution of FPGA-based platforms and the development of reusable digital IP for future ASIC implementations\nDrive engineering best practices, design quality, and technical improvements across the development lifecycle\nRequirements:\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline, or equivalent practical experience\n6+ years of professional experience in complex FPGA or ASIC digital logic design\nExpert-level proficiency in SystemVerilog RTL design (mandatory)\nExtensive experience defining digital architectures and microarchitectures for complex hardware systems\nProven track record of independently delivering complex digital IP or subsystems from specification to implementation\nDeep understanding of RTL optimization, logic synthesis, static timing analysis (STA), and timing closure\nStrong experience optimizing digital designs for deterministic latency, high clock frequencies, resource utilization, and power efficiency\nAdvanced knowledge of synchronous digital design, CDC, clocking architectures, and hardware interfaces\nStrong understanding of FPGA and/or ASIC development methodologies and implementation constraints\nExperience with simulation-based verification and debugging of complex digital systems\nAbility to evaluate architectural trade-offs, resolve challenging technical issues, and guide implementation decisions\nStrong technical leadership, analytical, and communication skills\nEnglish proficiency sufficient for effective collaboration within an international engineering team\nDesirable:\nExtensive experience with AMD/Xilinx FPGA architectures, particularly AMD Versal\nAdvanced experience with AMD Vivado, FPGA implementation, and timing closure\nFamiliarity with Synopsys VCS, Siemens Questa, and related verification/debugging tools\nExperience with ASIC digital IP development and FPGA-to-ASIC design considerations\nExperience designing complex DSP pipelines, waveform generation engines, or real-time control architectures\nDeep understanding of deterministic, nanosecond-scale timing and synchronization\nExperience with high-speed interfaces such as AXI, PCIe, DDR, or proprietary interconnects\nExperience with performance, area, and power (PPA) optimization\nKnowledge of Python, Tcl, or other languages used for EDA workflow automation\nExperience leading technical design reviews or mentoring senior engineers\nBackground in quantum computing, semiconductor development, telecommunications, high-performance instrumentation, or similar advanced technology domains\nWhat’s in it for you?\nFlexible working hours\nHome office option\n5 weeks of holiday\n5 sick days\nMultisport Card\nMeal allowance\nInternal trainings including workshops and seminars\nPaid certifications and technical as well as soft-skills training\nPossibility to participate in international conferences\nFresh fruit, coffee, and a weekly company breakfast in the office\nLoyalty bonus after 5, 10, 15 and more years with the company\nReferral bonus programme\nCorporate events including team building, outdoor activities, Christmas party, health week, summer ice cream, and more\nHybrid and remote working options available across our Czech offices in Prague, Hradec Králové, and Zlín\nAbout us:\nAt Ciklum, we are always exploring innovations, empowering each other to achieve more, and engineering solutions that matter. With us, you’ll work with cutting-edge technologies, contribute to impactful projects, and be part of a One Team culture that values collaboration and progress.\nWith delivery centers in Prague, Hradec Králové, and Zlín, our Czech team delivers end-to-end solutions across industries. Here, innovation thrives through collaboration, and every idea drives our partners' success.\nExplore, empower, engineer with Ciklum!\nInterested already? We would love to get to know you! Submit your application. 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