{"id":3365498,"url":"https://alion.io/job/cirrus-logic-2027-internship-formal-verification-engineer","title":"2027 Internship - Formal Verification Engineer","company":{"id":449717,"name":"Cirrus Logic","domain":"cirrus.com","url":"https://alion.io/company/cirrus-logic","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":{"grade":"B","score":70,"open_postings":116,"ghost_share":0.414,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":63,"computed_at":"2026-10-29T05:49:05Z"}},"role":"Hardware","role_family":"Hardware","seniority":"intern","employment_type":"internship","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-10-27T19:02:21Z","employer_posted_date":"2026-10-27","last_verified_at":"2026-10-29T05:22:51Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":1},"description":"Cirrus Logic is seeking an intern candidate for our Formal Verification team in Austin, TX. This position is focused on applying Formal Verification to digital designs. It is available to students currently enrolled in a MS or PhD program in Electrical and Computer Engineering. Candidate must be available for full-time employment during the internship.\nResponsibilities\nSupport the formal verification team to follow, and improve, defined methodology practices.\nDevelop test plans and verification methodologies to formally verify the microarchitecture and design.\nPerform failure analysis and resolution, coverage analysis, and population.\nImplement and improve functional and formal verification. \nRequired Skills and Qualifications:\nMaster’s or PhD degree in Electrical or Computer Engineering\nKnowledge in designing and implementing verification environments for module-level designs.\nExcellent communication skills and a collaborative approach to working with team members.\nProficiency in System Verilog.\nFamiliarity with scripting languages such as Python, Perl, TCL, Bash.\nExperienced or knowledge in UVM or equivalent methodologies.\nKnowledge in formal property languages such as SVA.\nKnowledge in property-based model-checking.\nKnowledgeable in signal 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