{"id":1621787,"url":"https://alion.io/job/cirrus-logic-dft-engineer-ce-64000920","title":"DFT Engineer (CE-64000920)","company":{"id":449717,"name":"Cirrus Logic","domain":"cirrus.com","url":"https://alion.io/company/cirrus-logic","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":{"grade":"B","score":77,"open_postings":112,"ghost_share":0.295,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":63,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"junior","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States","Chandler, United States","Greensboro, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":76000,"max_usd":147000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":468},"experience_years_min":2,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"SystemVerilog","optional":true},{"name":"Verilog","optional":true},{"name":"VHDL","optional":true}],"status":"live","first_seen_at":"2026-06-17T18:52:51Z","employer_posted_date":"2026-06-17","last_verified_at":"2026-10-18T11:48:55Z","board_verified":true,"closed_at":null,"days_open":122,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":122},"description":"As a DFT engineer in our mixed signal audio development team, you will be performing initial test planning, inserting memory BIST and scan, improving coverage, and delivering test patterns to our product test group. You will be working on industry leading mixed-signal SoC’s for consumer mobile audio markets, supporting several expanding product lines.\nResponsibilities:\nWork within a collaborative team environment to define, implement, and review DFT features.\nYou will generate, insert, and verify Memory BIST logic.\nPerform scan insertion and ATPG pattern generation.\nHelp develop and review DFT timing and equivalence checking constraints.\nPerform MBIST and ATPG pattern verification with gate level simulations.\nIdentify and improve any test coverage gaps.\nPerform test cost planning and analysis.\nDeliver MBIST and ATPG patterns to the product test group and support silicon bringup on the ATE.\nRequired Skills and Qualifications:\nMSEE with 2+ years of experience or BS with relevant industry experience.\nPossess strong hands on working knowledge on ASIC DFT design and verification.\nExperience in industry standard EDA tools for DFT such as FastScan, TestKompress, TetraMAX, Test Compiler etc.\nPreferred Skills and Qualifications:\nExperience with Verilog, System Verilog, or VHDL.\nUnderstanding of low power test techniques and architectures.\nKnowledge of scripting languages such as Perl, Python, or TCL.\nExperience with synthesis, static timing analysis, and developing timing constraints.\nStrong oral and written communication skills.\nExperience with flows and automation.\nWork independently as well as part of a team.\nHave a curious and inquiring mind with the commitment to follow through on getting answers.\nExperience with debugging and root causing silicon problems.","description_format":"text","description_chars":1783,"description_truncated":false,"requirements":{"experience_years_min":2,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United 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