{"id":3699807,"url":"https://alion.io/job/cirrus-logic-fpga-implementation-engineer-jr","title":"FPGA Implementation Engineer (JR)","company":{"id":449717,"name":"Cirrus Logic","domain":"cirrus.com","url":"https://alion.io/company/cirrus-logic","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":{"grade":"B","score":70,"open_postings":117,"ghost_share":0.419,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":63,"computed_at":"2026-11-05T05:54:30Z"}},"role":"Hardware","role_family":"Hardware","seniority":"junior","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"MATLAB","optional":false},{"name":"Python","optional":false},{"name":"Simulink","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"Synplify Pro","optional":true},{"name":"Xilinx Vivado","optional":true}],"status":"live","first_seen_at":"2026-11-03T19:04:56Z","employer_posted_date":"2026-11-03","last_verified_at":"2026-11-05T04:56:47Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":1},"description":"As an FPGA Implementation Engineer in our mixed-signal audio development team, you will perform the synthesis of ASIC designs onto FPGA platforms and ensure the quality of the design. You will work on complex FPGA prototyping systems and will help drive improvements in prototyping methodology across the division.\nResponsibilities:\nHelp deliver FPGA Platforms to internal groups to enable software development, and hardware-software pre-silicon validation.\nPorting ASIC-specific code and models into FPGA-friendly models.\nDefine and run functional tests to prove the FPGA builds prior to FPGA distribution.\nPerform FPGA synthesis, Implementation and Static Timing Analysis for complex ASIC designs.\nDevelop and maintain smoke tests to guarantee the quality of the deliverables from revision to revision.\nTest the digital chip RTL from a user perspective on FPGA platforms.\nDesign and implement equivalent analog models to model the final ASIC analog front end.\nIntroduce model-based designing methods with the help of Simulink or Matlab framework and representation.\nRequired Skills and Qualifications:\nMaster's degree in Electrical Engineering, Computer Science, or similar field and 3+ years of directly related experience.\nExperience using FPGAs and an understanding of how FPGA design differs from ASIC design.\nProficient in operating the simulation and modeling equipment including the design tools.\nKnowledge of Verilog, System Verilog, and digital design concepts.\nVerification/validation techniques and methodologies, including strong debugging skills.\nFamiliar with common on-chip bus protocols such as AMBA (AXI, AHB, APB) and communication protocols such as SPI, I2C, I2S, and UART.\nExperience with Scripting for Hardware development (Python/Tcl)\nPreferred Skills and Qualifications:\nExperience in FPGA flows - Synthesis, Place & Route, and Timing closure, with emphasis on Synopsys Synplify and Xilinx Vivado.\nUnderstanding of common FPGA primitives such as memories, I/O pads, BUFG, and MMCMs.\nExperience with Object-oriented programming (OOP) in Python.\nExperience with Floorplanning and advanced timing closure techniques.\nFamiliar with lab equipment such as Oscilloscope, Signal Generators and Logic Analyzers.\nSolid documentation, communication, and interpersonal skills.\nWork to tight and variable time scales.","description_format":"text","description_chars":2329,"description_truncated":false,"requirements":{"experience_years_min":3,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Headphones & Audio"],"lifecycle":[{"event":"open","at":"2026-11-03T19:08:11Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 4 · green card filings: 4","filings_12m":4,"filings_prev_12m":4,"green_card_filings_12m":4,"median_offered_wage_usd":150000,"route":null,"cap_exempt":false,"checked_at":"2026-10-29T16:27:21+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":2}],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":1,"expected_fill_days":63,"reasons":["conf:0","velocity","win:early","comp:junior,brand"],"computed_at":"2026-11-05T05:54:30Z"},"pay":null,"html_url":"https://alion.io/job/cirrus-logic-fpga-implementation-engineer-jr","json_url":"https://alion.io/job/cirrus-logic-fpga-implementation-engineer-jr.json","meta":{"generated_at":"2026-11-05T08:40:51Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":11034,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-06T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":449717},"rest":"https://alion.io/mcp/rest/get_company?id=449717"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcirrus-logic-fpga-implementation-engineer-jr"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcirrus-logic-fpga-implementation-engineer-jr"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcirrus-logic-fpga-implementation-engineer-jr"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/cirrus-logic-fpga-implementation-engineer-jr\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcirrus-logic-fpga-implementation-engineer-jr"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3699807}},{"tool":"search_jobs","arguments":{"company":"cirrus.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3699807},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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