{"id":1621826,"url":"https://alion.io/job/cirrus-logic-staff-design-verification-engineer","title":"Staff Design Verification Engineer","company":{"id":449717,"name":"Cirrus Logic","domain":"cirrus.com","url":"https://alion.io/company/cirrus-logic","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":{"grade":"B","score":71,"open_postings":113,"ghost_share":0.398,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":63,"computed_at":"2026-10-20T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States","Chandler, United States","Greensboro, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":147000,"max_usd":268000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":527},"experience_years_min":7,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false}],"status":"live","first_seen_at":"2026-04-15T16:52:38Z","employer_posted_date":"2026-04-15","last_verified_at":"2026-10-20T06:43:56Z","board_verified":true,"closed_at":null,"days_open":187,"trust":{"level":"ghost","repost_count":0,"flags":["stale","company_stale"],"days_open":187},"description":"We are seeking an experienced and innovative Design Verification Engineer to join a world-class silicon design verification team. This role partners closely with digital and analog designers, systems and applications engineers, firmware/software teams, and manufacturing test to deliver high-quality mixed-signal IC solutions. You will be responsible for end-to-end functional verification across block-level and chip-level designs, contributing to advanced verification methodologies and infrastructure.\nThis position offers exposure to multiple verification domains including UVM-based testbench development, formal verification, hardware emulation/acceleration, gate-level simulations, and software-driven verification in a highly collaborative and technically rigorous environment.\nResponsibilities:\nDevelop comprehensive verification plans aligned with design and system requirements.\nPerform functional verification of custom mixed-signal ASICs at block and chip level.\nDesign and implement UVM-based testbenches, including infrastructure, scoreboards, checkers, and assertions.\nCreate directed and constrained-random test suites to ensure robust functional coverage.\nImplement, analyze, and drive functional and code coverage, including coverage closure.\nConduct failure analysis, regression triage, and debug, resolving functional and timing-related issues.\nRun and debug gate-level simulations, including timing violations and back-annotation issues.\nDevelop and maintain digital and mixed-signal behavioral models to support verification.\nSupport verification flow and infrastructure development, including regressions and automation.\nCollaborate cross-functionally with digital/analog design, systems, applications, firmware/software, and manufacturing test teams.\nContribute to both pre-silicon verification and post-silicon validation efforts.\nProactively improve verification methodologies, processes, and best practices.\nRequired Knowledge, Skills, and Experience:\nBachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field.Bachelor’s with 7+ years of relevant experience.\nMaster’s with 5+ years of relevant experience.\nPhD with 3+ years of relevant experience.\nSignificant industry experience in silicon design and/or ASIC verification.\nStrong proficiency with HDLs: Verilog and/or VHDL.\nStrong proficiency with HVLs: SystemVerilog with UVM (or OVM/AVM/Vera).\nSolid understanding of digital design principles and system architecture.\nHands-on experience with:Testbench architecture and stimulus generation.\nRegression execution and debug.\nCoverage analysis and closure.\nAbility to work effectively in a cross-disciplinary, team-oriented environment.\n\nPreferred Knowledge, Skills, and Experience:\nExperience verifying mixed-signal ASICs in complex SoC environments.\nKnowledge of signal processing concepts relevant to mixed-signal designs.\nExperience with SystemVerilog Assertions (SVA).\nExposure to or hands-on experience with:\nFormal verification\nHardware emulation or acceleration\nSoftware-driven verification\nDemonstrated ability to evaluate, debug, and improve verification flows and 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cards)"],"filings_for_role_12m":2}],"liveness":{"score":8,"band":"cold","label":"Long shot","p_open":1,"p_active":0.3,"p_room":0.28,"age_days":187,"expected_fill_days":63,"reasons":["conf:2","velocity","ghost","win:tail","crowd:brand"],"computed_at":"2026-10-20T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/cirrus-logic-staff-design-verification-engineer","json_url":"https://alion.io/job/cirrus-logic-staff-design-verification-engineer.json","meta":{"generated_at":"2026-10-20T08:23:25Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per 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