{"id":2279725,"url":"https://alion.io/job/cisco-systems-asic-analog-engineer","title":"ASIC Analog Engineer","company":{"id":90,"name":"Cisco Systems","domain":"cisco.com","url":"https://alion.io/company/cisco-systems","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":92,"open_postings":264,"ghost_share":0.011,"stale_share":0.436,"repost_share":0.068,"time_to_fill_p50_days":16,"computed_at":"2026-10-12T06:55:09Z"}},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India","Pune, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":24000,"max_usd":56000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":712},"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Linux","optional":true}],"status":"live","first_seen_at":"2026-10-09T00:00:00Z","employer_posted_date":"2026-10-09","last_verified_at":"2026-10-12T21:38:53Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"What You'll Do\nWe are looking for a versatile and motivated Layout Engineer to join Cisco’s Silicon One Optics group an Engineering Team. In this role, you will support the physical implementation of high-performance analog and mixed-signal circuits for next-generation 100G, 200G, and 400G per lambda optical interconnect solutions.\nYou will contribute to all phases of physical design-from concept through tapeout-primarily for block-level layouts while assisting with top-level integration. Working closely with circuit designers, packaging engineers, process teams, and product engineers, you will help develop robust, manufacturable layouts that meet performance, reliability, area, and schedule goals.\nSpecific responsibilities include:\nSupport layout development and physical implementation of analog, mixed-signal circuits, high-speed interfaces (including SerDes and PAM4), and supporting digital blocks\nParticipate in block-level floor planning, placement, routing, and integration for sophisticated mixed-signal ICs\nCollaborate with circuit designers to translate schematics and performance targets into optimized physical layouts\nOptimize layouts for electrical performance, matching, parasitic, signal/power integrity, thermal behavior, yield, and manufacturability\nEnsure compliance with all foundry design rules (DRC, LVS, ERC, density, EM/IR, and reliability requirements)\nAssist in integration across analog, digital, and high-speed domains, including support for top-level assembly of SerDes, PAM4 paths, clocking, and control logic\nReview post-layout extraction results and support simulation closure\nFollow best practices for symmetry, shielding, isolation, and signal integrity\nPartner with packaging and product teams on bump planning, pad ring, ESD structures, and package integration\nIdentify and help resolve layout-related issues impacting performance, yield, or production readiness\nParticipate in layout reviews and provide feedback on feasibility, tradeoffs, and tapeout risks\nCollaborate with CAD teams to improve layout flows, automation, and efficiency\nSupport tapeout readiness, including database checks and signoff\nAssist senior engineers with mentoring more junior layout team members and embrace strong layout methodology\nSupport silicon bring-up, debug, and failure analysis for layout-related issues\nWho You’ll Work With\nAs a Layout Engineer in the Client Optics Group (COG) Engineering Team, you will collaborate with a multidisciplinary team including analog/mixed-signal circuit designers, digital designers, verification engineers, package engineers, process technologists, CAD specialists, reliability experts, and post-silicon validation teams.\nYou will partner with architects and designers during concept and planning phases, chip in to layout execution during design, work with signoff teams prior to tapeout, and support debug efforts post-silicon when layout-related issues arise. This role is a great opportunity to grow while helping deliver high-speed electrical IPs such as SerDes, PAM4 interfaces, D2D PHY, clocking subsystems, and control logic.\nWho You Are\nBachelor’s degree in Electrical Engineering or related field (Master’s preferred)\n4 to 5 years proven experience in custom IC layout for analog, mixed-signal, and high-speed designs\nSolid technical skills with a curiosity about growing into layout leadership; strong foundation in matching, symmetry, shielding, parasitic control, thermal management, and signal integrity\nGood knowledge of device-level layout techniques (common-centroid, interdigitation, guard rings, isolation structures)\nProficiency with industry-standard tools such as Cadence Virtuoso and Calibre (or equivalent)\nUnderstanding of DRC, LVS, ERC, parasitic extraction, EM/IR analysis, and physical signoff flows\nFamiliarity with ASIC/SoC tapeout processes is helpful\nExperience with scripting (Python, Perl, or TCL) for layout automation is a plus\nComfortable working in Linux environments\nExcellent analytical, problem-solving, communication, and partnership skills\nDemonstrated ability to chip in optimally and grow as a technical leader in a fast-paced environment\nAbility to work as a team player with cross-functional teams spread across geo-locations.\nMinimum Qualifications\nBachelor’s or Master’s or equivalent experience in Electrical Engineering or equivalent field\n3+ years of layout design experience in analog, mixed-signal, or high-speed IC development\nHands-on experience supporting block-level layout efforts through tapeout\nStrong skills in custom layout design, physical verification, and parasitic-aware implementation\nExperience with Cadence or similar custom layout tools\nWhy Cisco?\nAt Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.\nFueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.\nWe are Cisco, and our power starts with you.\nDisclaimer\nTo ensure that we hire the best talent in the right way, we follow a strict hiring process and recently, Cisco has been made aware of fraudulent recruiters claiming to be from the company. Please be advised that any communication from Cisco about careers will:\nbe in direct response to an application you have submitted through the company career site\nbegin with screening or an interview\noriginate from a Cisco email address, and\nbe conducted across email, phone, or WebEx\nCisco will never make a job offer without conducting an interview process or ask you for money in any way. If you have been requested to apply for a role or have received an offer from a site other than https://careers.cisco.com or cisco.wd5.myworkday.com, do not provide any personal identifying information, including your Aadhaar or other personal identifying number, birth certificate, banking information, driver's license, or passport.\nIf you are the target of a recruiting scam, consider filing a report with your local law enforcement authorities. Cisco bears no responsibility, and cannot be held liable, for any claims, damages, expenses, or other inconvenience resulting from or in any way connected to recruiting scams.","description_format":"text","description_chars":6738,"description_truncated":false,"requirements":{"experience_years_min":4,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"India","iso":"IN","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Cybersecurity","Government","Endpoint Security","Observability & APM"],"lifecycle":[{"event":"open","at":"2026-10-11T11:07:32Z"}],"visa":[],"liveness":{"score":85,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.847,"p_room":1,"age_days":3,"expected_fill_days":16,"reasons":["conf:2","win:early","comp:brand"],"computed_at":"2026-10-12T06:55:09Z"},"pay":null,"html_url":"https://alion.io/job/cisco-systems-asic-analog-engineer","json_url":"https://alion.io/job/cisco-systems-asic-analog-engineer.json","meta":{"generated_at":"2026-10-12T23:18:46Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":38262,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-13T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":90},"rest":"https://alion.io/mcp/rest/get_company?id=90"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcisco-systems-asic-analog-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcisco-systems-asic-analog-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcisco-systems-asic-analog-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/cisco-systems-asic-analog-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcisco-systems-asic-analog-engineer"}]}