{"id":681714,"url":"https://alion.io/job/cisco-systems-asic-engineering-design-verification-leader-systemverilog-python-c-and-uvm-8-12-years-pune","title":"ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)","company":{"id":90,"name":"Cisco Systems","domain":"cisco.com","url":"https://alion.io/company/cisco-systems","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":85,"open_postings":256,"ghost_share":0.031,"stale_share":0.473,"repost_share":0.094,"time_to_fill_p50_days":25,"computed_at":"2026-10-31T05:58:55Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Pune, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":35000,"max_usd":78000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":796},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-05-22T00:00:00Z","employer_posted_date":"2026-05-22","last_verified_at":"2026-10-31T01:56:33Z","board_verified":true,"closed_at":null,"days_open":162,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":162},"description":"Meet the Team\nCisco’s Client Optics Group (COG) designs & delivers the high-speed optical transceivers, and platforms that power Cisco's core data center networking solutions. We specialize in the design and integration of cutting-edge IM/DD optics and silicon photonic platforms that enable customers to deploy industry-leading optical technologies within data center with unprecedented speed, capacity, and reliability. Come join us and take part in shaping COG’s ground-breaking optical solutions by designing, developing, and testing some of the most advanced pluggable, and Co-packaged Optics (CPO) being developed in the industry.\nYou will work with Cisco's outstanding Silicon Photonics team. Our team is responsible for driving the development and optimization of optical transceivers & modules (800G,1.6T & beyond) that seamlessly integrate with Cisco's routing, switching, and datacenter platforms, enabling customers to build scalable, high-performance networks that support emerging technologies including AI/ML workloads, and next-generation data center architectures.\nYour Impact\nAs a Verification Engineer, you will work with a diverse team of engineers spanning multiple disciplines. At the concept phase you will create verification documentation and work with senior engineers to help with defining the verification methodology and developing testbench components. During the initial design phase, you will be a part of block level verification and then you will transition to full chip verification. You will run verification at block & chip level with various high-speed IPs integrated like ODSP, D2D IP, SerDes XSR, SerDes PAM4 integrated drivers/TIA, and control functions. You will develop functional coverage models, assertions, and debug complex verification issues within a UVM-based framework. Prior to tapeout you will run functional scenarios with CPU FW loaded and verify functionality at the CPU sub-system level. You may be involved in FPGA verification. Post Silicon you will be involved in ATE test plan and test vector generation, ATE testing and release to production.\nDevelop testbench components for Silicon Photonics subsystems. Proven ability to build UVM components (agents, drivers, monitors, scoreboards, sequences) and implement constrained-random and directed test strategies\nAbility to understand coverage metrics and functional specifications\nUnderstand and implement verification scenarios per full chip analog and digital verification test plans\nAnalyse coverage, add scenarios to enhance coverage and debug functional simulations, add corner verification cases and identify and resolve functional bugs\nFW/C-Coding and verification of CPU sub-systems with FW\nMust have good knowledge of Python and C. Develop scripts for automated analysis and reports\nGood understanding of RTL digital design and DFT (Design for Test) principles\nExcellent organizational, teamwork, and communication skills\nMinimum Qualifications\nBachelor’s or Masters in Electronics Engineering (or equivalent/related)\n8-12 years of functional verification experience\nStrong skills in SystemVerilog, Python, C and UVM methodology\nFamiliarity with UVM phases, configuration mechanisms, factory overrides, and reuse across block, subsystem, and SoC-level verification\nGood understanding of CPU sub-systems, FPGA, ODSP & integrated transceiver features, SerDes, Ethernet, D2D PHY IP & Protocols\nExperience with RTL design, simulation tools, (e.g., Synopsys, Cadence, Mentor Graphics) and ASIC design flow\nYou must be a team player and be able to drive decisions quickly with consensus building.\nStrong analytical, problem-solving and debugging skills\nStrong teamwork, communication, and organizational skills\nWhy Cisco?\nAt Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.\nFueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.\nWe are Cisco, and our power starts with you.","description_format":"text","description_chars":4568,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Network Security","Unified Communications","Network Equipment","Observability & APM"],"lifecycle":[{"event":"open","at":"2026-09-10T23:38:12Z"}],"visa":[],"liveness":{"score":8,"band":"cold","label":"Long shot","p_open":1,"p_active":0.27,"p_room":0.28,"age_days":162,"expected_fill_days":25,"reasons":["conf:4","stale_co","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-31T05:58:55Z"},"pay":null,"html_url":"https://alion.io/job/cisco-systems-asic-engineering-design-verification-leader-systemverilog-python-c-and-uvm-8-12-years-pune","json_url":"https://alion.io/job/cisco-systems-asic-engineering-design-verification-leader-systemverilog-python-c-and-uvm-8-12-years-pune.json","meta":{"generated_at":"2026-10-31T13:32:30Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":21013,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-01T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":90},"rest":"https://alion.io/mcp/rest/get_company?id=90"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcisco-systems-asic-engineering-design-verification-leader-systemverilog-python-c-and-uvm-8-12-years-pune"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcisco-systems-asic-engineering-design-verification-leader-systemverilog-python-c-and-uvm-8-12-years-pune"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcisco-systems-asic-engineering-design-verification-leader-systemverilog-python-c-and-uvm-8-12-years-pune"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/cisco-systems-asic-engineering-design-verification-leader-systemverilog-python-c-and-uvm-8-12-years-pune\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcisco-systems-asic-engineering-design-verification-leader-systemverilog-python-c-and-uvm-8-12-years-pune"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":681714}},{"tool":"search_jobs","arguments":{"company":"cisco.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":681714},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}