{"id":3053366,"url":"https://alion.io/job/cisco-systems-asic-engineering-technical-leader-8","title":"ASIC Engineering Technical Leader","company":{"id":90,"name":"Cisco Systems","domain":"cisco.com","url":"https://alion.io/company/cisco-systems","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":85,"open_postings":237,"ghost_share":0.03,"stale_share":0.456,"repost_share":0.101,"time_to_fill_p50_days":25,"computed_at":"2026-10-24T06:02:35Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hsinchu, Taiwan"],"countries":["TW"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":39000,"max_usd":88000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":741},"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-10-22T02:45:11Z","employer_posted_date":"2026-10-22","last_verified_at":"2026-10-22T23:09:28Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"ASIC DFT Technical Lead: MBIST\nJob Summary\nWe are looking for a highly experienced DFT Lead - MBIST to lead the architecture and silicon debug of advanced Memory Built-In Self-Test (MBIST) solutions for complex SoCs. The ideal candidate should have deep understanding on SRAM circuit, knowledge of memory Architecture, deep expertise in MBIST architecture, soft repair, hard repair, custom memory test algorithms, Vmin debug, post-silicon validation, yield improvement, and memory failure analysis.\nKey Responsibilities\nDevelop and optimize Mbist and memory testing architecture.\nLead the hardware implementation of defined architecture and methodology\nDevelop and optimize MBIST controllers for SRAM, register files, ROMs, and custom embedded memories.\nDefine and implement standard and custom MBIST algorithms based on memory architecture and product requirements.\nCollaborate with memory compiler and IP teams to understand memory internals and optimize test architecture.\nLead tape out sign-off for MBIST deliverables\nDebug Vmin-related memory failures and optimize test methodologies for low-voltage operation.\nLead post-silicon bring-up, memory diagnostics, and failure analysis.\nDrive yield improvement by analyzing manufacturing test data and identifying systematic memory failures.\nSupport customer-returned devices through RMA debug and root-cause analysis.\nDevelop custom diagnostic algorithms for memories not supported by standard MBIST implementations.\nLead technical reviews across cross-functional teams.\nWork closely with Design, Physical Design, Product Engineering, Reliability, and ATE teams to resolve silicon issues and improve product quality.\nRequired Skills\n12+ years of experience in DFT with strong focus on MBIST.\nExpert knowledge of MBIST architecture and structural DFT methodologies.\nExtensive experience with:MBIST controller design\nPSV and custom MBIST algorithms\nMarch algorithms and memory fault models\nBISR/BIRA\nMemory repair analysis\n\nDeep understanding of SRAM, ROM, register files, and custom embedded memory architectures.\nStrong expertise in:Vmin issue debugging\nSilicon bring-up\nPost-silicon validation\nYield debug\nFailure analysis\nRMA debug\n\nProficiency in Verilog/SystemVerilog and scripting (Python, Perl, or Tcl).\nKnowledge of IEEE 1149.1, IEEE 1500, and IEEE 1687.\nPreferred Qualifications\nExperience with advanced process nodes (7nm, 5nm, 3nm, or below).\nStrong background in custom memory architectures and non-standard MBIST implementations.\nProven experience leading DFT teams and driving silicon debug to production.\nExcellent problem-solving, technical leadership, and cross-functional communication skills.\nWe do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\nWhy Cisco?\nAt Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.\nFueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.\nWe are Cisco, and our power starts with you.","description_format":"text","description_chars":3672,"description_truncated":false,"requirements":{"experience_years_min":12,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"Taiwan","iso":"TW","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Network Security","Unified Communications","Endpoint Security","Observability & APM"],"lifecycle":[{"event":"open","at":"2026-10-22T02:45:11Z"}],"visa":[],"liveness":{"score":99,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.993,"p_room":1,"age_days":2,"expected_fill_days":25,"reasons":["conf:30","wave","velocity","win:early","comp:brand"],"computed_at":"2026-10-24T06:02:35Z"},"pay":null,"html_url":"https://alion.io/job/cisco-systems-asic-engineering-technical-leader-8","json_url":"https://alion.io/job/cisco-systems-asic-engineering-technical-leader-8.json","meta":{"generated_at":"2026-10-24T19:50:52Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":29004,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-25T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":90},"rest":"https://alion.io/mcp/rest/get_company?id=90"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcisco-systems-asic-engineering-technical-leader-8"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcisco-systems-asic-engineering-technical-leader-8"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcisco-systems-asic-engineering-technical-leader-8"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/cisco-systems-asic-engineering-technical-leader-8\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcisco-systems-asic-engineering-technical-leader-8"}]}