{"id":3066904,"url":"https://alion.io/job/cisco-systems-asic-engineering-technical-leader-9","title":"ASIC Engineering Technical Leader","company":{"id":90,"name":"Cisco Systems","domain":"cisco.com","url":"https://alion.io/company/cisco-systems","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":85,"open_postings":237,"ghost_share":0.03,"stale_share":0.456,"repost_share":0.101,"time_to_fill_p50_days":25,"computed_at":"2026-10-23T05:54:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India","Ahmedabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":38000,"max_usd":87000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":741},"experience_years_min":11,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Ansys RedHawk","optional":false},{"name":"Cadence Innovus","optional":false},{"name":"Formal Verification","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Siemens Calibre","optional":false},{"name":"Synopsys Formality","optional":false},{"name":"Synopsys PrimeTime","optional":false}],"status":"live","first_seen_at":"2026-10-21T00:00:00Z","employer_posted_date":"2026-10-21","last_verified_at":"2026-10-22T23:09:28Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"Meet The Team:\nOur creative and talented Physical Design team in Bangalore, India. As a member of this team you will be involved in creating next generation state-of-the-art networking chips in advanced process node. You will drive the backend process through the entire RTL 2 GDS Implementation flow including hierarchical floor planning, place & route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with special focus on performance & die size optimization.\nYour Impact:\nAnalyzes current generation quality and efficiency gaps to identify proper incremental or evolutionary changes to the existing physical design related Tools, Flow and Methodology.\nWork closely with various teams such as physical design, RTL, DFT, tool/flow owners, and EDA vendors to improve physical design methodologies.\nGood understanding of different CTS strategies and providing the feedback to Implementation Team.\nAs member of physical design team, drive methodologies and “best known methods” to streamline and automate physical design work.\nSTA setup, convergence methodology, reviews and sign-off for Multi-Mode and Multi-corner designs.\nGood at Timing ECO Implementation strategy development/convergence. Should have an experience in enabling the Tweaker/Primetime based ECO flows.\nWork on Automation scripts within STA tools for Methodology development Excellent debugging skills in implementation issues and ability to produce creative solutions.\nEvaluate multiple timing methodologies/tools on different designs and technology nodes.\nGood scripting skills (TCL/SHELL/PERL/Python) is a MUST\nMinimum Qualification:\nBachelor's or a Master’s Degree in Electrical or Computer Engineering required\nYou are an ASIC engineer with 11+ years of related work experience with a broad mix of technologies including:\nAll aspects of ASIC Physical implementation including Floor planning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.\nHierarchical design implementation approach, Timing closure, physical convergence.\nPower Integrity Analysis\nExperience with large designs (>100M gates) utilizing state of the art sub 16/14/7/5/3nm technologies.\nFamiliarity with various process related design issues including Design for Yield and Manufacturability, multi-Vt strategies.\nPreffered Qualifications:\nFloor planning and P&R tools: Cadence Innovus & Synopsys ICC2\nSynthesis Tools: Synopsys DC/FC\nFormal Verification : Synopsys Formality and Cadence LEC\nStatic Timing verification: Primetime-DMSA\nPower Integrity : Apache Redhawk\nPhysical Design Verification Synopsys ICV, Mentor Calibre\nScripting: TCL, Perl is required; Python is a plus\nWhy Cisco?\nAt Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.\nFueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.\nWe are Cisco, and our power starts with you.\nDisclaimer\nTo ensure that we hire the best talent in the right way, we follow a strict hiring process and recently, Cisco has been made aware of fraudulent recruiters claiming to be from the company. Please be advised that any communication from Cisco about careers will:\nbe in direct response to an application you have submitted through the company career site\nbegin with screening or an interview\noriginate from a Cisco email address, and\nbe conducted across email, phone, or WebEx\nCisco will never make a job offer without conducting an interview process or ask you for money in any way. If you have been requested to apply for a role or have received an offer from a site other than https://careers.cisco.com or cisco.wd5.myworkday.com, do not provide any personal identifying information, including your Aadhaar or other personal identifying number, birth certificate, banking information, driver's license, or passport.\nIf you are the target of a recruiting scam, consider filing a report with your local law enforcement authorities. Cisco bears no responsibility, and cannot be held liable, for any claims, damages, expenses, or other inconvenience resulting from or in any way connected to recruiting scams.","description_format":"text","description_chars":4774,"description_truncated":false,"requirements":{"experience_years_min":11,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"India","iso":"IN","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Network Security","Unified Communications","Endpoint Security","Observability & APM"],"lifecycle":[{"event":"open","at":"2026-10-22T08:21:54Z"}],"visa":[],"liveness":{"score":99,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.993,"p_room":1,"age_days":2,"expected_fill_days":25,"reasons":["conf:6","wave","velocity","win:early","comp:brand"],"computed_at":"2026-10-23T05:54:15Z"},"pay":null,"html_url":"https://alion.io/job/cisco-systems-asic-engineering-technical-leader-9","json_url":"https://alion.io/job/cisco-systems-asic-engineering-technical-leader-9.json","meta":{"generated_at":"2026-10-23T16:59:49Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":25761,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-24T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":90},"rest":"https://alion.io/mcp/rest/get_company?id=90"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcisco-systems-asic-engineering-technical-leader-9"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcisco-systems-asic-engineering-technical-leader-9"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcisco-systems-asic-engineering-technical-leader-9"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/cisco-systems-asic-engineering-technical-leader-9\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcisco-systems-asic-engineering-technical-leader-9"}]}