{"id":3537810,"url":"https://alion.io/job/cisco-systems-asic-layout-engineer","title":"ASIC Layout Engineer","company":{"id":90,"name":"Cisco Systems","domain":"cisco.com","url":"https://alion.io/company/cisco-systems","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":289,"ghost_share":0.048,"stale_share":0.464,"repost_share":0.097,"time_to_fill_p50_days":25,"computed_at":"2026-11-07T05:47:08Z"}},"role":"Hardware","role_family":"Hardware","seniority":"junior","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Yerevan, Armenia"],"countries":["AM"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":38000,"max_usd":92000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":769},"experience_years_min":2,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Quantus","optional":false},{"name":"Cadence Virtuoso","optional":false},{"name":"Python","optional":false},{"name":"Synopsys StarRC","optional":false},{"name":"Perl","optional":true}],"status":"live","first_seen_at":"2026-10-30T18:15:54Z","employer_posted_date":"2026-10-30","last_verified_at":"2026-11-07T05:56:05Z","board_verified":true,"closed_at":null,"days_open":7,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":7},"description":"Meet the Team\nWe develop the foundation IP behind the Cisco Silicon One platform, which powers the world's most advanced switches and routers. Our international team delivers the standard cell libraries and analog IP that Silicon One ASICs are built on, on groundbreaking process technology.\nAbout the Role\nWe are hiring an ASIC Engineer to design and verify standard cells for our next-generation ASICs on innovative FinFET and GAA nodes. You will build high-performance cell layouts, take them to clean physical verification, and run library QA checks before release. You will work closely with senior engineers and with the circuit design, characterization and physical design teams. This role offers broad hands-on exposure and a clear path to technical ownership.\nWhat You'll Do\nDesign standard cell layouts: logic, high-drive, clock, level shifter, tap/boundary and specialty cells.\nOptimize cell layouts for density, performance, power, EM and manufacturability.\nRun physical verification and fix issues to clean signoff: DRC, LVS, antenna, ERC and extraction.\nRun library QA checks and resolve view mismatches across GDS, LEF, Liberty, NDM and CDL.\nDevelop and maintain scripts for layout, verification and QA (Python, Tcl, SKILL).\nSupport analog/mixed-signal layout work with the mixed-signal team.\nSupport the characterization team with extraction and netlist QA, and help prepare library releases.\nDebug block-level layout and verification issues with the physical design and STA teams.\nTake part in layout and QA reviews and contribute to methodology improvements.\nMinimum Qualifications\nBachelor's + 3 years, Master's + 2 years, or PhD of related experience in Electrical Engineering, Computer Engineering or a related field.\nFirst hand standard cell or custom layout experience on FinFET nodes such as TSMC 7nm, 5nm, 3nm or 2nm.\nExperience with physical verification and extraction tools such as Calibre, ICV, StarRC or Quantus.\nProficiency in Cadence Virtuoso.\nPreferred Qualifications\nAnalog/mixed-signal design and layout experience, such as PLLs, LDOs, bandgaps, IOs or sensors, including matching, shielding and post-layout simulation.\nExperience with standard cell characterization and Liberty modeling, using tools such as PrimeLib, Liberate or SiliconSmart.\nExperience with library QA and view consistency checks (GDS, LEF, Liberty, CDL).\nExposure to library release: abstract/LEF and NDM generation and validation in P&R tools.\nScripting in Python, Tcl, SKILL or Perl for design automation.\nFamiliarity with EM/IR analysis and low-power cells (multi-Vt, power gating, retention).\nStrong written and spoken English, and experience working in multi-site teams.\nWhy Cisco?\nAt Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.\nFueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.\nWe are Cisco, and our power starts with you.","description_format":"text","description_chars":3527,"description_truncated":false,"requirements":{"experience_years_min":2,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[{"language":"English","level":"All levels","optional":true}]},"benefits":[],"hiring_locations":[{"name":"Armenia","iso":"AM","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Network Security","Unified Communications","Endpoint Security","Observability & APM"],"lifecycle":[{"event":"open","at":"2026-10-30T18:15:54Z"}],"visa":[],"liveness":{"score":62,"band":"ok","label":"Likely open","p_open":1,"p_active":0.619,"p_room":1,"age_days":7,"expected_fill_days":25,"reasons":["conf:5","stale_co","velocity","win:early","comp:junior,brand"],"computed_at":"2026-11-07T05:47:08Z"},"pay":null,"html_url":"https://alion.io/job/cisco-systems-asic-layout-engineer","json_url":"https://alion.io/job/cisco-systems-asic-layout-engineer.json","meta":{"generated_at":"2026-11-07T10:32:48Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":9546,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-08T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":90},"rest":"https://alion.io/mcp/rest/get_company?id=90"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcisco-systems-asic-layout-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcisco-systems-asic-layout-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcisco-systems-asic-layout-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/cisco-systems-asic-layout-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcisco-systems-asic-layout-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3537810}},{"tool":"search_jobs","arguments":{"company":"cisco.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3537810},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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