{"id":679908,"url":"https://alion.io/job/cisco-systems-design-verification-engineer-for-dft","title":"Design Verification Engineer for DFT","company":{"id":90,"name":"Cisco Systems","domain":"cisco.com","url":"https://alion.io/company/cisco-systems","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":92,"open_postings":174,"ghost_share":0.011,"stale_share":0.471,"repost_share":0.052,"time_to_fill_p50_days":15,"computed_at":"2026-09-29T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Tel Aviv, Israel","Israel"],"countries":["IL"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":136000,"max_usd":312000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1198},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-07-26T00:00:00Z","employer_posted_date":"2026-07-26","last_verified_at":"2026-09-29T11:53:11Z","board_verified":true,"closed_at":null,"days_open":66,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":66},"description":"Meet the Team\nWe are a leading Design for Test (DFT) group, delivering end-to-end solutions for Cisco’s flagship products, including Cisco Silicon One. Our chips are strategically placed in critical AI infrastructure, powering next-generation network devices and supporting advanced AI workloads.\nWe push the boundaries of technology by developing innovative DFT solutions that drive industry-leading programmability, scalability, test quality, and performance. Our team operates in a hybrid model, with three days a week in the office in Midtown Tel Aviv or Caesarea, fostering collaboration and technical excellence in a startup-like atmosphere within a stable, global corporation.\nRole Focus: We are looking for an experienced Design Verification engineer to join our DFT team and help establish and grow DFT DV activity in the Cisco SiliconOne DFT team. This role is relevant for engineers with experience in DV roles, either in DFT DV or in other verification domains, who are interested in becoming familiar with DFT design, verification methodologies, and the challenges of validating testability features in advanced silicon.\nYour Impact\nLead and drive DFT verification activities within the Cisco SiliconOne DFT team.\nDevelop verification plans, environments, checkers, assertions, and coverage models for DFT features.\nVerify DFT architecture and implementation in close collaboration with DFT, design, architecture, and verification teams.\nWork on verification of scan, MBIST, IJTAG/JTAG, test access mechanisms, DFT controllers, and related SoC-level test features.\nDebug complex pre-silicon issues across RTL, verification environments, and DFT logic.\nContribute to scalable methodologies, reusable verification components, and best practices for DFT DV.\nHelp bridge between general DV methodologies and DFT-specific design and verification needs.\nMinimum Qualifications\nB.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or a related field.\n5+ years of experience in design verification roles.\nStrong experience with SystemVerilog and UVM-based verification environments.\nExperience developing verification plans, coverage models, assertions, and debug flows.\nStrong communication skills and ability to work closely with cross-functional teams.\nMotivation to learn DFT concepts and become a key contributor in the DFT DV domain.\nPreferred Qualifications\nFamiliarity with DFT concepts such as scan insertion, memory BIST, ATPG, boundary scan, and silicon test flows.\nExperience with complex SoC verification, networking silicon, or high-performance AI-driven silicon.\nSystem-level understanding of large-scale chip architecture and integration.\nAbility to build new methodologies and establish verification activity from the ground up.\nHigh attention to detail, ownership mindset, and willingness to grow into new technical domains.\nWhy Cisco?\nAt Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.\nFueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.\nWe are Cisco, and our power starts with you.","description_format":"text","description_chars":3704,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"Israel","iso":"IL","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Network Security","Unified Communications","Network Equipment","Observability & APM"],"lifecycle":[{"event":"open","at":"2026-09-10T23:23:11Z"}],"liveness":{"score":15,"band":"cold","label":"Long shot","p_open":1,"p_active":0.433,"p_room":0.35,"age_days":65,"expected_fill_days":15,"reasons":["conf:4","velocity","win:tail","comp:brand"],"computed_at":"2026-09-29T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/cisco-systems-design-verification-engineer-for-dft","json_url":"https://alion.io/job/cisco-systems-design-verification-engineer-for-dft.json","meta":{"generated_at":"2026-09-30T00:26:12Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":233,"day_limit":5000,"remaining_today":4767,"minute_limit":60,"resets_at":"2026-10-01T00:00:00Z"}}}