{"id":1905490,"url":"https://alion.io/job/cisco-systems-memory-layout-design-engineer-3","title":"Memory Layout Design Engineer","company":{"id":90,"name":"Cisco Systems","domain":"cisco.com","url":"https://alion.io/company/cisco-systems","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":92,"open_postings":264,"ghost_share":0.011,"stale_share":0.436,"repost_share":0.068,"time_to_fill_p50_days":16,"computed_at":"2026-10-12T06:55:09Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Armenia"],"countries":["AM"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":36000,"max_usd":86000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1586},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-10-05T12:48:48Z","employer_posted_date":"2026-10-05","last_verified_at":"2026-10-12T03:56:00Z","board_verified":true,"closed_at":null,"days_open":6,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":6},"description":"This is a hybrid role with four days per week at Cisco’s Yerevan office.\nMeet the Team\nOur team is at the forefront of innovation, specializing in memory layout implementation for the Cisco Silicon One platform that powers the world’s most advanced switches and routers. We are a dynamic, international team dedicated to pushing the boundaries of high-performance networking technology. We offer a unique environment where technical excellence meets real-world impact. We value transparency, clear communication, and a collaborative spirit that bridges geographical divides to deliver ground breaking silicon solutions.\nYour Impact\nImplement high-quality memory layout implementation, specifically focusing on SRAM blocks to meet rigorous performance and reliability standards. Collaborate closely with international circuit design teams to translate schematics into robust physical designs that drive our core networking products. Perform post-layout simulations and implement necessary corrections to ensure DRC cleanliness and optimal integration with neighboring modules. Optimize layout designs for quality, visibility, and velocity to accelerate the delivery of critical silicon components.\nMinimum Qualifications\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.\n5+ years of total professional experience in physical design or layout.\nProven experience working with industry-standard EDA tools such as Cadence or Synopsys.\nExperience with advanced node technologies such as TSMC 22nm, 12nm, 7nm, 5nm, or 2nm.\nPreferred Qualifications\n3+ years of hands-on experience specifically in SRAM layout implementation.\nExperience working within a mixed-signal or custom design environment.\nProficiency in performing EMIR/ERC closure and providing technical support for successful tapeouts.\nBackground in circuit design, including reading schematics and running simulations.\nProficiency in scripting languages (Tcl, Python, or Perl) for design automation.\nStrong ability to communicate effectively in English, both written and spoken, to support international collaboration.\nDemonstrated ability to work both independently and within a cross-functional, multi-site team environment.\nWhy Cisco?\nAt Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.\nFueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.\nWe are Cisco, and our power starts with you.","description_format":"text","description_chars":3074,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[{"language":"English","level":"All levels","optional":true}]},"benefits":[],"hiring_locations":[{"name":"Armenia","iso":"AM","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Cybersecurity","Government","Endpoint Security","Observability & APM"],"lifecycle":[{"event":"open","at":"2026-10-05T12:48:48Z"}],"visa":[],"liveness":{"score":77,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.851,"p_room":0.9,"age_days":6,"expected_fill_days":16,"reasons":["conf:2","velocity","win:mid","comp:brand"],"computed_at":"2026-10-12T06:55:09Z"},"pay":null,"html_url":"https://alion.io/job/cisco-systems-memory-layout-design-engineer-3","json_url":"https://alion.io/job/cisco-systems-memory-layout-design-engineer-3.json","meta":{"generated_at":"2026-10-12T07:57:44Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":12738,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-13T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":90},"rest":"https://alion.io/mcp/rest/get_company?id=90"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcisco-systems-memory-layout-design-engineer-3"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcisco-systems-memory-layout-design-engineer-3"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcisco-systems-memory-layout-design-engineer-3"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/cisco-systems-memory-layout-design-engineer-3\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcisco-systems-memory-layout-design-engineer-3"}]}