{"id":3375514,"url":"https://alion.io/job/cisco-systems-senior-asic-layout-engineer","title":"Senior ASIC Layout Engineer","company":{"id":90,"name":"Cisco Systems","domain":"cisco.com","url":"https://alion.io/company/cisco-systems","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":234,"ghost_share":0.03,"stale_share":0.5,"repost_share":0.09,"time_to_fill_p50_days":26,"computed_at":"2026-11-01T06:10:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Yerevan, Armenia"],"countries":["AM"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":56000,"max_usd":129000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1936},"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Quantus","optional":false},{"name":"Cadence Virtuoso","optional":false},{"name":"Python","optional":false},{"name":"Synopsys StarRC","optional":false},{"name":"Verilog","optional":false},{"name":"Perl","optional":true},{"name":"Synopsys Fusion Compiler","optional":true}],"status":"live","first_seen_at":"2026-10-27T00:00:00Z","employer_posted_date":"2026-10-27","last_verified_at":"2026-11-01T09:49:02Z","board_verified":true,"closed_at":null,"days_open":5,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":5},"description":"Meet the Team\nWe develop the foundation IP behind the Cisco Silicon One platform, which powers the world's most advanced switches and routers. Our international team delivers the standard cell libraries and analog IP that Silicon One ASICs are built on, on groundbreaking process technology.\nAbout the Role\nWe are hiring an ASIC Engineer to own standard cell layout for our next-generation ASICs on innovative FinFET and GAA nodes. You will design and verify high-performance cells, drive physical verification to clean signoff, and own library quality from GDS to release. You will work closely with circuit design, characterization, physical design and foundry teams. As the senior technical owner, you will set direction, define methodology and mentor engineers on the team.\nWhat You'll Do\nDrive the layout architecture and design of standard cell libraries: logic, high-drive, clock, level shifter, tap/boundary and specialty cells.\nOwn the physical design of complex cells, optimizing for density, performance, power, EM and manufacturability.\nDrive physical verification to clean signoff: DRC, LVS, antenna, ERC, extraction and EM/IR.\nDefine and own library QA: keep GDS, LEF, Liberty, NDM, CDL and Verilog consistent and ready for signoff.\nDevelop and deploy automation for layout, verification and QA (Python, Tcl, SKILL).\nContribute to analog/mixed-signal IP design and layout alongside the mixed-signal team.\nWork with the characterization team on extraction, netlist QA and correlation; contribute to library release.\nLead block-level issue resolution and take part in chip-level debug with the physical design and STA teams.\nDrive layout and QA reviews, flag concerns early, and mentor engineers.\n\nMinimum Qualifications\nBachelor's + 7 years, Master's + 4 years, or PhD + 1 year of related experience in Electrical Engineering, Computer Engineering or a related field.\nFirst hand standard cell layout experience on advanced nodes such as TSMC 5nm, 3nm or 2nm.\nStrong physical verification and extraction experience, with tools such as Calibre, ICV, StarRC or Quantus.\nExperience with library QA and view consistency checks (GDS, LEF, Liberty, CDL).\nProficiency in Cadence Virtuoso.\nPreferred Qualifications\nAnalog/mixed-signal design and layout experience, such as PLLs, LDOs, bandgaps, IOs or sensors, including matching, shielding and post-layout simulation.\nExperience with standard cell characterization and Liberty modeling, using tools such as PrimeLib, Liberate or SiliconSmart.\nExperience with library release: abstract/LEF and NDM generation, packaging and validation in P&R tools such as Innovus, Fusion Compiler or ICC2.\nScripting in Python, Tcl, SKILL or Perl for design automation.\nExperience with EM/IR closure and low-power cells (multi-Vt, power gating, retention).\nExperience with IO/bump cell layout.\nStrong written and spoken English, and experience working in multi-site teams.\nWhy Cisco?\nAt Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.\nFueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.\nWe are Cisco, and our power starts with you.","description_format":"text","description_chars":3755,"description_truncated":false,"requirements":{"experience_years_min":4,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[{"language":"English","level":"All levels","optional":true}]},"benefits":[],"hiring_locations":[{"name":"Armenia","iso":"AM","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Network Security","Unified Communications","Endpoint Security","Observability & APM"],"lifecycle":[{"event":"open","at":"2026-10-28T02:35:12Z"}],"visa":[],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":5,"expected_fill_days":26,"reasons":["conf:1","stale_co","velocity","win:early","comp:brand"],"computed_at":"2026-11-01T06:10:25Z"},"pay":null,"html_url":"https://alion.io/job/cisco-systems-senior-asic-layout-engineer","json_url":"https://alion.io/job/cisco-systems-senior-asic-layout-engineer.json","meta":{"generated_at":"2026-11-01T12:33:00Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":19301,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-02T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":90},"rest":"https://alion.io/mcp/rest/get_company?id=90"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcisco-systems-senior-asic-layout-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcisco-systems-senior-asic-layout-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcisco-systems-senior-asic-layout-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/cisco-systems-senior-asic-layout-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcisco-systems-senior-asic-layout-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3375514}},{"tool":"search_jobs","arguments":{"company":"cisco.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3375514},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}