STA Methodology Engineer
First seen by Alion on Aug 19, 2026.
Job Description:
We are looking for a skilled STA Methodology Engineer to join the team working on and using the Statistical Timing Estimation Platform (STEP) internal gateway to timing data for silicon projection and correlation.
You will drive PVT-aware Fmax/Vmin estimation and be actively involved in post-silicon correlation and pre-silicon design closure across advanced technology nodes, collaborating with design, PnR, process technology, and silicon validation teams.
What You'll Do:
- Drive STA methodology development for statistical timing estimation infrastructure: timing closure flows, PVT scaling model integration, and silicon frequency projection.
- Develop and validate PVT (Process, Voltage, Temperature) scaling models for logic cells, RAMs, FCM, and wire delay leveraging Process Lookup Tables (PLUTs) for characterization across EOC/aging conditions.
- Analyze system-level performance metrics (Fmax, Vmin, MPE, MPW) and debug path-level timing reports critical paths, cell/wire margins, crosstalk, and part-to-part sensitivity.
- Correlate pre-silicon STA results with post-silicon measurements to build and refine silicon projection models.
- Integrate layout-driven timing effects into STEP flows: IR-drop, SPEF scaling, EM/IR/Noise reliability impacts, and aging derates (EOC_AGING).
- Validate quality of timing estimation data and contribute to SPICE-level verification of timing models.
Required Qualifications:
- 5 to 7 years of hands-on STA experience, preferably in advanced node (7nm, 5nm, 3nm) ASIC or GPU design.
- Deep understanding of system-level performance metrics: Fmax, Min Period (MPE), Min Pulse Width (MPW), setup/hold closure at signoff corners.
- Strong path-level timing analysis skills: reading and debugging STA signoff reports (PrimeTime or equivalent), cell delay, wire delay, clock path contributions, cell/wire margin analysis, derating (OCV/AOCV/POCV), jitter (DCD, PLL uncertainty), and part-to-part variation sensitivity.
- Experience with PVT variation analysis modeling Process, Voltage, and Temperature impact on Fmax and Vmin.
- Background in PnR flows: back-annotated SPEF, IR-drop-aware timing, and reliability effects (EM, noise, aging/EOC derates).
- Scripting proficiency in Python and/or Tcl for timing flow automation and data analysis.
Skills
Static Timing Analysis, Python, TCL, GPU, PnR, Scripting