{"id":1280272,"url":"https://alion.io/job/clarus-impact-network-sta-methodology-engineer","title":"STA Methodology Engineer","company":{"id":3801525,"name":"Clarus- Impact Network","domain":"clarusadvisers.com","url":"https://alion.io/company/clarus-impact-network","size_band":null,"is_staffing_agency":true,"employer_type":"agency","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, 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post-silicon correlation and pre-silicon design closure across advanced technology nodes, collaborating with design, PnR, process technology, and silicon validation teams.\n\nWhat You'll Do:\n\n- Drive STA methodology development for statistical timing estimation infrastructure: timing closure flows, PVT scaling model integration, and silicon frequency projection.\n\n- Develop and validate PVT (Process, Voltage, Temperature) scaling models for logic cells, RAMs, FCM, and wire delay leveraging Process Lookup Tables (PLUTs) for characterization across EOC/aging conditions.\n\n- Analyze system-level performance metrics (Fmax, Vmin, MPE, MPW) and debug path-level timing reports critical paths, cell/wire margins, crosstalk, and part-to-part sensitivity.\n\n- Correlate pre-silicon STA results with post-silicon measurements to build and refine silicon projection models.\n\n- Integrate layout-driven timing effects into STEP flows: IR-drop, SPEF scaling, EM/IR/Noise reliability impacts, and aging derates (EOC_AGING).\n\n- Validate quality of timing estimation data and contribute to SPICE-level verification of timing models.\n\nRequired Qualifications:\n\n- 5 to 7 years of hands-on STA experience, preferably in advanced node (7nm, 5nm, 3nm) ASIC or GPU design.\n\n- Deep understanding of system-level performance metrics: Fmax, Min Period (MPE), Min Pulse Width (MPW), setup/hold closure at signoff corners.\n\n- Strong path-level timing analysis skills: reading and debugging STA signoff reports (PrimeTime or equivalent), cell delay, wire delay, clock path contributions, cell/wire margin analysis, derating (OCV/AOCV/POCV), jitter (DCD, PLL uncertainty), and part-to-part variation sensitivity.\n\n- Experience with PVT variation analysis modeling Process, Voltage, and Temperature impact on Fmax and Vmin.\n\n- Background in PnR flows: back-annotated SPEF, IR-drop-aware timing, and reliability effects (EM, noise, aging/EOC derates).\n\n- Scripting proficiency in Python and/or Tcl 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