{"id":2641905,"url":"https://alion.io/job/clera-senior-silicon-engineer-3","title":"Senior Silicon Engineer","company":{"id":2706,"name":"Clera","domain":"getclera.com","url":"https://alion.io/company/clera","size_band":"11-50","is_staffing_agency":true,"employer_type":"agency","is_intermediary":false,"listed_via":null,"ats_vendor":"Ashby","truth_index":{"grade":"B","score":80,"open_postings":30,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":6,"computed_at":"2026-10-15T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Francisco, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":200000,"max":300000,"currency":"USD","period":"year","gross":null,"usd_annual":300000},"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cocotb","optional":false},{"name":"Formal Verification","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-10-15T17:20:13Z","employer_posted_date":"2026-10-15","last_verified_at":"2026-10-15T19:07:01Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"About the Role\nLead silicon design for an AI accelerator, taking designs from FPGA prototypes through ASIC tapeout and bring-up. As a senior member of a small hardware team, you will shape technical direction across architecture, RTL, verification, and tooling, working closely with PCB, interconnect, software, and systems teams.\nWhat You'll Do\nLead FPGA prototype development and optimization, from design specifications through deployment on working hardware.\n\nDesign and review synthesizable RTL for an ASIC, with a focus on clean microarchitecture.\n\nBuild and improve lint, simulation, synthesis, timing, and verification flows for rapid iteration and tapeout readiness.\n\nMake architecture decisions across compute datapaths, memory systems, on-chip interconnect, and control logic.\n\nDrive design through tapeout, bring-up, and delivery milestones, contributing hands-on during critical periods.\n\nMentor teammates and help grow the silicon engineering team.\n\nWhat We're Looking For\nAt least 8 years of experience in digital design or silicon engineering, building RTL, FPGA prototypes, or ASICs.\n\nExperience shipping synthesizable SystemVerilog or Verilog in production silicon or FPGA designs, and taking FPGA designs from RTL through synthesis, place-and-route, and deployment to working hardware.\n\nStrong understanding of digital design, including pipelining, clocks, resets, latency, throughput, and microarchitecture.\n\nExperience designing compute datapaths and memory systems with bandwidth and latency constraints.\n\nHands-on experience with simulation, linting, synthesis, SDC constraints, timing closure, and CDC verification.\n\nExperience automating hardware flows with Python, Tcl, Make, Nix, or similar tools, plus background in AI accelerators or low-level AI kernels.\n\nTapeout experience, high-speed interfaces, formal verification, UVM, cocotb, firmware, or systems-level hardware drivers are valuable.\n\nCompensation & Benefits\nBase salary is $200,000 to $300,000 USD annually. Visa sponsorship is available.\nLocation\nFull-time, on-site role in San Francisco, United States. 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