Design Verification Engineer
Confirmed on the employer's own hiring board on Oct 20, 2026. First seen by Alion on Jul 28, 2026.
**Please note this role is only open to candidates currently located in and with working rights in the DE**
Location: Preferably based at one of our UK design centres (Bristol or Cambridge).
Seniority: Engineer, Senior Engineer
Welcome to Codasip
AtCodasip, we’re redefining the future of computing. Following a bold strategic pivot toward cyber-resilient semiconductor architectures, we are building next-generation processors and systems where security is embedded at the very core by design, not as an afterthought. As we expand our portfolio of secure, CHERI -enabled technologies and focus on delivering architecture-first security solutions, there has never been a more exciting time to join. We are embarking on clean-sheet designs and expanding the teams of engineers who can establish high-quality working practices as they explore new ground. Be part of a global team shaping the next era of secure computing where innovation, ownership, and impact go hand in hand.
The impact you’ll make
- Verify RISC-V processors and extensions
- Develop verification solutions (e.g., test benches and test bench components, stimulus generation, formal environments)
- Collaborate with other engineers in a team responsible for the delivery of all verification activities related to a component or subsystem from start to finish
- Define verification strategies for blocks and sub-systems, identifying and utilising the right tools
- Review technical specifications, providing feedback from a verification perspective
- Run simulations, hunt bugs and complete root cause analysis of complex issues
- Define, estimate, prioritise and track your own work
- Track and report verification metrics
- Craft automated verification flows
What You Bring to The Table
- Commercial experience with functional processor verification methodologies as applied to CPU or other ASIC verification (simulators, test generation, coverage collection, gate-level simulation, etc.)
- Knowledge of verifying CPU architectures or other IP
- Fluency and the ability to write clear and concise code in languages like SystemVerilog, Python, C++, Rust, etc.
- Past verification ownership of a design block
- User knowledge of Linux to enable automation of common tasks
- Knowledge of versioning tools (Git, SVN)
- Knowledge of RISC-V Architecture
- Good knowledge of computer systems and architecture
- Analytical thinking and team collaboration skills
- Ability to work effectively across teams to debug issues and find root causes
Our DE design center in Munich, launched in 2020, is driving innovation in cutting-edge RISC-V CPU development. We’re designing high-performance, low-power CPU cores entirely from scratch to power some of the most exciting applications - think high-performance supercomputers and next-generation embedded systems. This is a unique chance to work on clean-sheet designs that push technological boundaries and make a real impact.
We’re looking for Verification Engineers to help bring our vision to life. You’ll be a key part of verifying complex, state-of-the-art CPUs, including advanced out-of-order processors. Taking ownership of portions of the design, you’ll apply a range of verification methodologies and play a vital role in setting high standards for a brand-new platform.
This is an opportunity to collaborate with an international team spanning Europe, working alongside world-class engineers across disciplines to solve challenges and pioneer new ideas. If you’re a bright, driven self-starter who thrives on innovation and wants to build something great, we’d love to hear from you.
Join us in Munich and be part of a team redefining what’s possible in CPU design and cyber-resilient semiconductor architectures.
Get to Know Us
Codasip announces strategic pivot and divestiture
CHERI-RISC-V standardisation status - Tariq Kurd | CHERITech'25