{"id":1266143,"url":"https://alion.io/job/connectpro-management-consultants-principal-engineersenior-manager","title":"Principal Engineer/Senior Manager","company":{"id":3808036,"name":"Connectpro Management Consultants","domain":"connectproconsultants.com","url":"https://alion.io/company/connectpro-management-consultants","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":27000,"max_usd":62000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":741},"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"HPC","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-09-07T12:13:16Z","employer_posted_date":null,"last_verified_at":"2026-09-07T12:13:16Z","board_verified":false,"closed_at":null,"days_open":47,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":47},"description":"Principal Engineer / Senior Manager Digital Design\n\nWe are looking for an experienced Digital Design Lead to drive the architecture, microarchitecture, RTL design, and development of next-generation UA Link Switch products within the Memory Interface Division (MID). The ideal candidate will bring deep expertise in high-speed digital system design and SoC development, with a proven track record delivering complex silicon products from architecture through production.\n\nThe role involves leading high-speed digital design initiatives and delivering scalable, high-bandwidth, low-latency interconnect solutions for AI, HPC, and memory-centric systems.\n\nKey Requirements:\n\n- 15+ years of ASIC/SoC design experience.\n\n- Strong expertise in RTL Design (Verilog/System Verilog), SoC architecture, and subsystem integration.\n\n- Experience with switching fabrics, NoC, high-speed interconnects, memory subsystems, and high-bandwidth data movement architectures.\n\n- Hands-on knowledge in modern ASIC development flows including synthesis, STA, low-power design methodologies, and silicon bring-up.\n\n- Proven track record leading complex chip development programs from architecture to production and influence cross-functional teams.\n\nPreferred Skills:\n\n- Experience with PCIe, CXL, Ethernet, UCIe, SerDes, AI/HPC interconnects, or memory interface technologies.\n\n- Exposure to large-scale SoCs for networking, compute, storage, or memory applications.\n\n- Strong understanding of system-level architecture and board-level considerations for high-speed designs.\n\n- Strong leadership, mentoring, and cross-functional collaboration skills.\n\n- Experience leading geographically distributed engineering teams.\n\nLeadership Expectations:\n\n- Provide technical vision and architectural guidance for UA Link Switch development.\n\n- Drive innovation in high-bandwidth, low-latency interconnect solutions.\n\n- Mentor and grow engineering talent across the organization.\n\n- Establish engineering best practices and ensure execution excellence across design teams.\n\nSkills\nASIC, SoC, RTL Design, VLSI, Verilog, System Verilog, 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