{"id":2599155,"url":"https://alion.io/job/credo-senior-digital-design-engineer","title":"Senior Digital Design Engineer","company":{"id":1958633,"name":"Credo","domain":"credosemi.com","url":"https://alion.io/company/credosemi","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"HiBob","truth_index":{"grade":"B","score":75,"open_postings":14,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":130000,"max":200000,"currency":"USD","period":"year","gross":null,"usd_annual":200000},"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"C++","optional":true},{"name":"MATLAB","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-07-09T16:45:17Z","employer_posted_date":"2026-10-15","last_verified_at":"2026-10-17T14:27:15Z","board_verified":true,"closed_at":null,"days_open":99,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":99},"description":"Team Credo is looking for a Senior PHY RTL Design Engineer to join our mission to transform connectivity at scale. In this role, you will be responsible for the RTL architecture, design, implementation, and verification of advanced SerDes PHY Digital Signal Processing (DSP) blocks used in next-generation networking, AI, data center, and high-performance computing products. The ideal candidate possesses strong digital design fundamentals, hands-on RTL development experience, and a good understanding of high-speed SerDes architecture. This position will be onsite at our San Jose, CA HQ. \nBase salary range is $130,000 - $200,000 a year. The base salary offer will depend on factors such as education, experience, training, skills, qualifications, and location. This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits.\n\nWhy Credo\nPurpose: We invest in what matters. From meaningful-future shaping projects to competitive compensation, we empower you to grow your career while making a lasting impact.\nPeople: Connection starts within. We collaborate, celebrate wins, and create an environment where everyone can do their best work.\n Possibilities: Our belief shapes what’s next. Our technology powers the most reliable and energy-efficient connections around the world - and our team powers new products and markets that come next.\nResponsibilities\nDefine RTL micro-architecture for digital PHY and SerDes DSP functions.\nDevelop synthesizable RTL for DSP blocks (FFE, DFE, adaptive equalization, CDR loops), working with system architects and algorithm teams to translate DSP algorithms into RTL.\nOptimize designs for performance, power, area, and latency.\nVerify DSP modules and debug functional issues; support synthesis, timing closure, CDC/RDC analysis, and DFT integration.\nAnalyze silicon bring-up data with validation teams to resolve issues, and support PHY integration and system-level debugging.\nQualifications\nBasic QualificationsBS/MS/PhD in Electrical Engineering, Computer Engineering, or a related field, with five or more years of digital design experience (or equivalent expertise for senior candidates).\nStrong RTL development skills using SystemVerilog, including fixed-point arithmetic RTL implementation.\nExperience designing high-speed communication or DSP hardware.\nExperience with the ASIC development flow (e.g., Lint, CDC/RDC, synthesis, timing analysis) and familiarity with EDA tools from Synopsys, Cadence, or Siemens.\nStrong debugging and problem-solving skills. \nPreferred Qualifications\nExperience with high-speed SerDes standards such as PCIe and Ethernet, and an understanding of SerDes receiver and transmitter architectures.\nUnderstanding of DSP algorithms (e.g., LMS adaptation, timing recovery), with MATLAB or C/C++ modeling experience.\nFamiliarity with Python or other scripting languages.\nKnowledge of mixed-signal PHY architecture and analog/digital interfaces, including experience with mixed-signal PHY simulations.\nExperience supporting silicon bring-up and post-silicon validation, with exposure to advanced process nodes (7nm, 5nm, 3nm, or beyond).\nAbout Credo\nCredo’s mission is to transform connectivity at scale through fast, reliable, and energy-efficient system solutions. Our high-speed copper and optical interconnect products deliver industry-leading power and performance at up to 1.6T to meet the ever-expanding data infrastructure demands of AI. \nOur product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. Credo innovations enable our customers to connect the systems that connect the world.\n\nCredo is committed to creating an inclusive environment for all employees and welcome applicants from diverse backgrounds without regard to race, color, religion, gender, sex, gender identity, sexual orientation, pregnancy, marital status, national origin, ethnicity, genetic information, age, disability, veteran status, or any other legally protected basis. If you have a disability or special need that requires accommodation to navigate our website or complete the application process, email .","description_format":"text","description_chars":4349,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Equity"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Artificial Intelligence","Cybersecurity","Hardware"],"lifecycle":[{"event":"open","at":"2026-10-15T07:54:35Z"}],"visa":[],"liveness":{"score":11,"band":"cold","label":"Long shot","p_open":1,"p_active":0.328,"p_room":0.35,"age_days":99,"expected_fill_days":36,"reasons":["conf:1","stale_co","win:tail"],"computed_at":"2026-10-17T05:46:00Z"},"pay":{"stated_usd_annual":200000,"is_top_pay":true},"html_url":"https://alion.io/job/credo-senior-digital-design-engineer","json_url":"https://alion.io/job/credo-senior-digital-design-engineer.json","meta":{"generated_at":"2026-10-17T15:22:08Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":20769,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-18T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":1958633},"rest":"https://alion.io/mcp/rest/get_company?id=1958633"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcredo-senior-digital-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcredo-senior-digital-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcredo-senior-digital-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/credo-senior-digital-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcredo-senior-digital-design-engineer"}]}