{"id":1280166,"url":"https://alion.io/job/cyclad-hardware-verification-engineer-soc-semiconductor-ip","title":"Hardware Verification Engineer – SoC / Semiconductor IP","company":{"id":895,"name":"Cyclad","domain":"cyclad.eu","url":"https://alion.io/company/cyclad","size_band":"51-200","is_staffing_agency":true,"employer_type":"agency","is_intermediary":false,"listed_via":null,"ats_vendor":"Recruitify","truth_index":{"grade":"B","score":81,"open_postings":36,"ghost_share":0,"stale_share":0.75,"repost_share":0,"time_to_fill_p50_days":46,"computed_at":"2026-10-01T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":null,"work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"inferred","locations":[],"countries":[],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Formal Verification","optional":false},{"name":"Python","optional":false},{"name":"SystemC","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false}],"status":"live","first_seen_at":"2026-09-25T12:44:25Z","employer_posted_date":"2026-09-25","last_verified_at":"2026-10-01T02:58:15Z","board_verified":true,"closed_at":null,"days_open":6,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":6},"description":"In Cyclad we work with top international IT companies in order to boost their potential in delivering outstanding, cutting edge technologies that shape the world of the future. Currently, we are looking for a Hardware Verification Engineer to join an engineering team working on advanced semiconductor technologies, including System-on-Chip (SoC) and chiplet-based architectures.\nIn this role, you will be responsible for developing and executing verification strategies for complex hardware IP and interconnect solutions. You will work closely with engineers across different technical areas to help ensure the functionality, reliability, and quality of sophisticated hardware products..\nProject information:\nLocation: Kraków (2 days from the office)\nRemuneration: 24 000 - 26 000 gross CoE\nProject languages: English\nKey Responsibilities:\nDefine, document, develop, and execute RTL verification tests and coverage strategies for highly configurable IP using Python and C++, with support for different RTL simulation environments and EDA platforms.\nMaintain, optimize, and extend existing verification workflows and infrastructure.\nImprove verification metrics, increase automation, and identify opportunities to make testing more efficient.\nDevelop verification components such as Bus Functional Models (BFMs), monitors, and related elements used within hardware verification environments.\nRequirements:\nAt least 4 years of professional experience working as a Hardware Verification Engineer.\nGood understanding of RTL design and hardware verification technologies, with experience in languages such as VHDL, Verilog, SystemVerilog, SystemC, C++, and Python.\nStrong practical experience developing and using verification methodologies and infrastructure, including VIPs, UVM, test environments, and EDA tools.\nKnowledge or practical experience with formal verification methodologies would be an advantage.\nExperience with Shell scripting and automation.\nUnderstanding of hardware communication and interconnect protocols, including AMBA, OCP, or comparable technologies.\nA structured and quality-focused approach to engineering, combined with curiosity, independence, attention to detail, and a strong focus on delivering results.\nAbility to collaborate effectively within a multidisciplinary engineering team.\nWillingness to travel to France for business trips.\nFluent English is required.\nMaster’s degree or PhD in Engineering, Computer Science, or a related technical field.\nWe offer:\nPremium Lux Med medical and dental care package.\nMultisport card.\nLife insurance.\nMonthly lunch allowance of PLN 450.\nUnlimited paid time off.","description_format":"text","description_chars":2632,"description_truncated":false,"requirements":{"experience_years_min":4,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[{"language":"English","level":"Advanced (C1)","optional":false}]},"benefits":["Life insurance"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Incident Response"],"lifecycle":[{"event":"open","at":"2026-09-26T02:34:27Z"}],"liveness":{"score":38,"band":"fade","label":"Fading","p_open":1,"p_active":0.379,"p_room":1,"age_days":5,"expected_fill_days":46,"reasons":["conf:2","agency","stale_co","velocity","win:early","comp:brand"],"computed_at":"2026-10-01T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/cyclad-hardware-verification-engineer-soc-semiconductor-ip","json_url":"https://alion.io/job/cyclad-hardware-verification-engineer-soc-semiconductor-ip.json","meta":{"generated_at":"2026-10-01T13:12:11Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":4826,"day_limit":5000,"remaining_today":174,"minute_limit":60,"resets_at":"2026-10-02T00:00:00Z"}}}