{"id":3066415,"url":"https://alion.io/job/cyient-dft-engineer","title":"DFT Engineer","company":{"id":59344,"name":"Cyient","domain":"cyient.com","url":"https://alion.io/company/cyient","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"services","is_intermediary":false,"listed_via":null,"ats_vendor":"Zwayam","truth_index":{"grade":"A","score":88,"open_postings":24,"ghost_share":0,"stale_share":0.5,"repost_share":0,"time_to_fill_p50_days":46,"computed_at":"2026-11-06T05:58:05Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Linux","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys TestMAX","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Tessent","optional":false},{"name":"Unix","optional":false},{"name":"Verification & Validation","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-09-01T10:47:02Z","employer_posted_date":"2026-10-22","last_verified_at":"2026-11-06T22:44:41Z","board_verified":true,"closed_at":null,"days_open":66,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":66},"description":"Job Summary\nWe are seeking a highly skilled DFT Engineer to support Qualcomm SoC development programs. The candidate will be responsible for DFT architecture implementation, scan insertion, ATPG generation, MBIST/LBIST integration, pattern validation, and silicon bring-up activities for complex mobile, automotive, and high-performance SoC designs.\nKey Responsibilities\nDFT Implementation\n·Develop and implement DFT architectures for advanced SoC designs.\n·Perform scan insertion and scan chain validation using industry-standard EDA tools.\n·Integrate and verify DFT features including:\noScan Compression\noEDT\noMBIST\noLBIST\noBoundary Scan (JTAG/IEEE 1149.1)\noOCC (On-Chip Clock Controller)\nATPG & Pattern Generation\n·Generate ATPG patterns for stuck-at, transition, path-delay, and bridge fault coverage.\n·Analyze fault coverage and optimize pattern count.\n·Debug DRC violations and pattern simulation failures.\nVerification & Validation\n·Perform RTL and gate-level DFT verification.\n·Validate scan functionality and test modes through simulation.\n·Work closely with design, physical design, and verification teams for DFT signoff.\nSilicon Bring-up & Production Support\n·Support first silicon bring-up and failure analysis.\n·Collaborate with ATE teams for production test development.\n·Debug manufacturing test issues and improve yield.\nCross-Functional Collaboration\n·Interface with Architecture, RTL Design, Physical Design, STA, and Product Engineering teams.\n·Participate in design reviews and contribute to DFT methodology improvements.\nRequired Skills\nTechnical Skills\n·Strong understanding of:\noScan Architecture\noScan Compression\noATPG\noMBIST/LBIST\noJTAG/Boundary Scan\noFault Modeling\noDFT Signoff Methodologies\nEDA Tools\nExperience with one or more:\n·Synopsys DFT Compiler\n·Synopsys TestMAX / TetraMAX\n·Cadence Modus\n·Siemens Tessent Scan\n·Tessent MBIST\n·Tessent Diagnosis\nLanguages & Scripting\n·Verilog/SystemVerilog\n·TCL\n·Perl\n·Python\n·Unix/Linux Shell Scripting\nDebug Skills\n·Scan chain debugging\n·ATPG pattern analysis\n·Silicon failure diagnosis\n·Coverage closure\nPreferred Qualifications\n·Experience on Qualcomm Snapdragon, Automotive, AI/ML, DSP, or Modem SoCs.\n·Exposure to low-power DFT methodologies.\n·Knowledge of UPF/CPF and power-aware testing.\n·Understanding of advanced-node designs (7nm, 5nm, 4nm, 3nm).\n·Prior silicon bring-up and yield improvement experience.\nEducation\n·Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Computer Engineering, or a related field.\nKeywords\nDFT, Scan Insertion, ATPG, MBIST, LBIST, JTAG, Boundary Scan, Tessent, Modus, DFT Compiler, TestMAX, Silicon Bring-up, OCC, Compression, Fault Coverage, SoC, Qualcomm, Snapdragon.","description_format":"text","description_chars":2704,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["IT Consulting & Digital Transformation","Engineering Services"],"lifecycle":[{"event":"open","at":"2026-10-22T08:09:47Z"}],"visa":[],"liveness":{"score":23,"band":"cold","label":"Long shot","p_open":1,"p_active":0.414,"p_room":0.55,"age_days":65,"expected_fill_days":46,"reasons":["conf:1","stale_co","velocity","win:tail","comp:brand"],"computed_at":"2026-11-06T05:58:05Z"},"pay":null,"html_url":"https://alion.io/job/cyient-dft-engineer","json_url":"https://alion.io/job/cyient-dft-engineer.json","meta":{"generated_at":"2026-11-06T23:16:10Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":2516,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-07T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":59344},"rest":"https://alion.io/mcp/rest/get_company?id=59344"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcyient-dft-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcyient-dft-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcyient-dft-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/cyient-dft-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcyient-dft-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3066415}},{"tool":"search_jobs","arguments":{"company":"cyient.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3066415},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}