{"id":2773210,"url":"https://alion.io/job/cyient-physical-design-engineer","title":"Physical Design Engineer","company":{"id":59344,"name":"Cyient","domain":"cyient.com","url":"https://alion.io/company/cyient","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Zwayam","truth_index":{"grade":"B","score":75,"open_postings":4,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Synopsys Design Compiler","optional":false},{"name":"Synopsys Fusion Compiler","optional":false},{"name":"Synopsys IC Validator","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"Synopsys StarRC","optional":false}],"status":"live","first_seen_at":"2026-08-04T07:32:32Z","employer_posted_date":"2026-10-17","last_verified_at":"2026-10-17T16:50:25Z","board_verified":true,"closed_at":null,"days_open":74,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":74},"description":"Key Responsibilities\nPhysical Design Implementation\nOwn complete Physical Design flow from synthesis handoff to GDSII.\nPerform Floor planning, Power Planning, Placement, CTS, Routing, Physical Optimization, and ECO implementation.\nDrive block-level and full-chip design closure on advanced FinFET nodes.\nExecute congestion analysis and optimization to achieve PPA targets.\nTiming Closure\nPerform timing analysis using Synopsys PrimeTime.\nResolve setup, hold, transition, capacitance, and noise violations.\nDrive MCMM timing closure across multiple corners and modes.\nImplement timing ECOs and optimize critical timing paths.\nPhysical Verification & Signoff\nRun and debug DRC/LVS/ERC violations using industry-standard signoff tools.\nAnalyze and resolve physical design issues impacting manufacturability.\nEnsure successful tapeout readiness.\nPower & Signal Integrity\nPerform IR Drop and EM analysis.\nOptimize power distribution networks.\nPerform signal integrity checks and noise analysis to ensure robust silicon performance.\nDesign Optimization\nDrive area, power, and performance optimization.\nWork closely with RTL, DFT, STA, and P&R teams to achieve design convergence.\nSupport Design-for-Manufacturability (DFM) requirements.\nRequired Technical Skills\nSynopsys Tool Expertise\nStrong expertise in:Synopsys ICC2\nFusion Compiler\nPrimeTime\nStarRC\nIC Validator\nDesign Compiler (Good to Have)\n\nPhysical Design Skills\nFloorplanning\nPower Planning\nPlacement Optimization\nClock Tree Synthesis (CTS)\nRouting & Optimization\nTiming Closure\nECO Closure\nSignoff Closure\nLow Power Implementation\nFinFET Experience\nMandatory hands-on experience in:16nm FinFET\n12nm FinFET\n7nm FinFET\n5nm FinFET (Preferred)\n\nSignoff Expertise\nMCMM Timing Closure\nSignal Integrity Analysis\nCrosstalk Analysis\nIR Drop Analysis\nEM Analysis\nDRC/LVS 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