RTL Design Engineer

Cyient • IT Consulting & Digital Transformation • Engineering Services • Verilog • SystemVerilog • 10 hours ago
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Location
In office (Bengaluru)

Confirmed on the employer's own hiring board on Oct 22, 2026. First seen by Alion on Jul 21, 2026. Cyient scores B on the Alion truth index.

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Cyient

Cyient provides engineering, geospatial and network services to global industries. Its work spans aerospace design, rail signalling, utilities mapping and semiconductor engineering. The company also manufactures electronic hardware for specialist customers.
cyient.com • HQ: Hyderabad, India • IT Consulting & Digital Transformation • Engineering Services • 1001-5000 employees • Est. 1991
Tech stack of Cyient
  • Develop RTL designs using Verilog/SystemVerilog based on architecture specifications.
  • Define and implement digital micro-architecture for SoC/IP blocks.
  • Design and integrate modules related to:
    • Motor Control Systems
    • Industrial Communication Interfaces
    • Embedded Controllers
    • DMA, Interrupt Controllers
    • GPIO, Timers, PWM Modules
    • UART, SPI, I2C, CAN, Ethernet Interfaces
  • Perform RTL coding, linting, CDC and quality checks.
  • Analyze architecture specifications and convert them into RTL implementation.
  • Support functional verification teams during simulation and debug activities.
  • Collaborate with DFT teams for scan insertion and testability requirements.
  • Work with Synthesis and Physical Design teams to close implementation issues.
  • Participate in RTL reviews, design reviews, and code reviews.
  • Prepare RTL documentation and design specifications.
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