{"id":3066421,"url":"https://alion.io/job/cyient-senior-staff-engineer-ams-layout","title":"Senior Staff Engineer - AMS Layout","company":{"id":59344,"name":"Cyient","domain":"cyient.com","url":"https://alion.io/company/cyient","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Zwayam","truth_index":{"grade":"B","score":83,"open_postings":15,"ghost_share":0,"stale_share":0.667,"repost_share":0,"time_to_fill_p50_days":44,"computed_at":"2026-10-25T05:49:26Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":20000,"max_usd":47000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1625},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Siemens Calibre","optional":false},{"name":"Synopsys IC Compiler II","optional":false}],"status":"live","first_seen_at":"2026-10-22T05:01:37Z","employer_posted_date":"2026-10-22","last_verified_at":"2026-10-25T09:55:46Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"Job Summary**\nWe are seeking a highly skilled and experienced Senior Staff Engineer - AMS Layout to join our team. In this role, you will be responsible for leading and executing the physical layout of complex Analog/Mixed-Signal (AMS) integrated circuits, ensuring performance, reliability, and manufacturability for cutting-edge semiconductor designs.\nJob Responsibilities**\n* Lead and perform the physical layout design of highly complex Analog/Mixed-Signal (AMS) blocks and full chips, including custom circuits, RF, power management, and high-speed interfaces.\n* Collaborate closely with design engineers to understand circuit requirements, identify layout challenges, and propose optimal layout solutions.\n* Perform floor planning, block-level layout, and top-level integration, ensuring efficient utilization of silicon area and adherence to design specifications.\n* Conduct comprehensive physical verification (DRC, LVS, DFM, ERC) using industry-standard tools and resolve identified issues.\n* Must have exposure of solving critical latchup, Antenna and density related fixes.\n* Perform parasitic extraction and back-annotation for post-layout simulations, working with design teams to ensure performance targets are met.\n* Develop and implement innovative layout techniques to optimize performance, power, and area for critical AMS circuits.\n* Mentor and provide technical guidance to junior layout engineers, fostering a collaborative and knowledge-sharing environment.\n* Contribute to the development and improvement of layout methodologies, best practices, and automation scripts.\n* Participate in design reviews and provide constructive feedback to ensure high-quality layout delivery.\n* Interface with foundry representatives to understand process rules and ensure designs are compliant with manufacturing requirements.\nJob Qualifications**\n* Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field.\n* 10+ years of hands-on experience in Analog/Mixed-Signal (AMS) IC layout design.\n* Expert proficiency in using industry-standard EDA tools such as Cadence Virtuoso Layout Suite (XL), Mentor Graphics Calibre, Synopsys IC Compiler II.\n* Deep understanding of semiconductor physics, fabrication processes, and their impact on layout design.\n* Extensive experience with various AMS layouts, including ADCs, DACs, PLLs, LDOs, Op-amps, high-speed interfaces, and RF blocks.\n* Solid knowledge of deep submicron process technologies (e.g., 28nm, 16nm, 7nm, 5nm).\n* Strong understanding of layout effects on circuit performance (e.g., matching, coupling, IR drop, electro-migration, latch-up).\n* Experience with scripting languages like Perl, Python, or Skill for layout automation is highly desirable.\n* Excellent problem-solving, analytical, and communication skills.\n* Ability to work independently and as part of a multi-disciplinary team in a fast-paced environment.\n* Prior experience in a leadership or mentorship role is a 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