{"id":3066416,"url":"https://alion.io/job/cyient-senior-staff-engineer-digital-design","title":"Senior Staff Engineer - Digital Design","company":{"id":59344,"name":"Cyient","domain":"cyient.com","url":"https://alion.io/company/cyient","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Zwayam","truth_index":{"grade":"B","score":83,"open_postings":15,"ghost_share":0,"stale_share":0.667,"repost_share":0,"time_to_fill_p50_days":44,"computed_at":"2026-10-24T06:02:35Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Leuven, Belgium"],"countries":["BE"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":101000,"max_usd":207000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":601},"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false}],"status":"live","first_seen_at":"2026-07-08T13:31:09Z","employer_posted_date":"2026-10-22","last_verified_at":"2026-10-24T18:52:44Z","board_verified":true,"closed_at":null,"days_open":108,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":108},"description":"Summary:\nDesigns advanced digital building blocks for various applications, incl. but not limited to power management, low-power & low-voltage applications.\nResponsibilities:\nMicro-architecture specification development and design documentation\nRTL development using VHDL or Verilog/System Verilog, according to functional requirements and following design guidelines\nLint, CDC, Synthesis, & Power Optimization\nSoft and hard IP identification, selection and integration\nTiming and power constraints development\nCollaboration with analog design team for mixed-signal designs\nCollaboration with verification team in verification plan development and debug\nCollaboration with physical design team to close the design on timing and power\nMinimum Qualification:\n4 years experience in RTL development\nAdvanced knowledge of RTL design using VHDL or Verilog/SystemVerilog\nBasic knowledge of UVM Testbench development\nStrong communication and presentation skills in English\nPreferred Qualification:\nKnowledge of mixed signal concepts\nHands-on experience with synthesis and/or place-and-route\nAble to work in a team\nGood problem solving skills and being able to implement solutions autonomously\nUnderstanding of Dutch language","description_format":"text","description_chars":1216,"description_truncated":false,"requirements":{"experience_years_min":4,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[{"language":"Dutch","level":"All levels","optional":true},{"language":"English","level":"All levels","optional":false}]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["IT Consulting & Digital Transformation","Engineering Services"],"lifecycle":[{"event":"open","at":"2026-10-22T08:09:47Z"}],"visa":[],"liveness":{"score":12,"band":"cold","label":"Long shot","p_open":1,"p_active":0.445,"p_room":0.28,"age_days":107,"expected_fill_days":44,"reasons":["conf:3","stale_co","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-24T06:02:35Z"},"pay":null,"html_url":"https://alion.io/job/cyient-senior-staff-engineer-digital-design","json_url":"https://alion.io/job/cyient-senior-staff-engineer-digital-design.json","meta":{"generated_at":"2026-10-24T21:21:13Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":31315,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-25T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":59344},"rest":"https://alion.io/mcp/rest/get_company?id=59344"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcyient-senior-staff-engineer-digital-design"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcyient-senior-staff-engineer-digital-design"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcyient-senior-staff-engineer-digital-design"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/cyient-senior-staff-engineer-digital-design\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcyient-senior-staff-engineer-digital-design"}]}