{"id":3445329,"url":"https://alion.io/job/cystems-logic-physical-design-engineer-sunnyvale-ca","title":"Physical Design Engineer- Sunnyvale, CA","company":{"id":695880,"name":"Cystems Logic","domain":"cystemslogic.com","url":"https://alion.io/company/cystemslogic","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SmartRecruiters","truth_index":null},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"staff","employment_type":"contractor","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Sunnyvale, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":123000,"max_usd":239000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":1394},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[],"status":"live","first_seen_at":"2026-10-29T04:12:13Z","employer_posted_date":"2026-10-29","last_verified_at":"2026-10-30T14:26:39Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"Hi,\nJob Title: Physical Design Engineer\nLocation- Sunnyvale, CA- Onsite\nDuration: Long Term contract\nWe have below longterm contract and onsite job opening.\nIf you are interested, Please send your updated resume with below details...ASAAP\nYOUR CURRENT LOCATION:\nVISA STATUS:\nAVAILABILITY:\nRELOCATE: YES / NO\nEXPECTED RATE ALL INC ON RATE ON C2C/1099:\nKey Responsibilities:\nNeed a PDE with front end experience who is good with Synthesis, PDE flow and placement optimization.\nWe are hiring an experienced Physical Design Engineer to join a high-performing silicon engineering team supporting one of the world's leading technology organizations in Sunnyvale, CA. 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improvements.\nRequired Qualifications :\n· Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.\n· Strong hands-on experience in ASIC/SoC physical design with 10+ years of industry experience.\n· Expertise in RTL synthesis and timing optimization.\n· Solid experience with floorplanning for advanced technology nodes.\n· Strong understanding of netlist optimization and physical implementation methodologies.\n· Experience collaborating with RTL/design teams to improve design quality and implementation efficiency.\n· Excellent communication and cross-functional collaboration skills.\nPreferred Skills :\n· Experience with industry-standard EDA tools for synthesis and physical design.\n· Strong understanding of timing, congestion, power, and area optimization techniques.\n· Experience working on high-performance CPU, GPU, AI/ML, or networking SoCs is a plus\nAll your information will be kept confidential according to EEO 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