{"id":35543,"url":"https://alion.io/job/d-matrix-senior-staff-design-verification-engineer","title":"Sr. Staff Design Verification Engineer","company":{"id":8215,"name":"d-Matrix","domain":"d-matrix.ai","url":"https://alion.io/company/d-matrix","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Ashby","truth_index":{"grade":"A","score":88,"open_postings":7,"ghost_share":0,"stale_share":0.286,"repost_share":0,"time_to_fill_p50_days":83,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":175000,"max":265000,"currency":"USD","period":"year","gross":null,"usd_annual":265000},"salary_estimate":null,"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"C++","optional":true},{"name":"SystemC","optional":true}],"status":"live","first_seen_at":"2025-04-03T05:24:56Z","employer_posted_date":"2025-04-03","last_verified_at":"2026-10-18T08:27:53Z","board_verified":true,"closed_at":null,"days_open":563,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":562},"description":"At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration.\nWe value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together, we can help shape the endless possibilities of AI.\nRole Overview\nd-Matrix is building a company and culture designed to last - one grounded in transparency, inclusiveness, and intellectual honesty, where continuous learning is part of the job. We've built the industry's first highly programmable in-memory computing architecture, applicable across a broad range of applications from cloud to edge. In this role, you'll work on a groundbreaking architecture alongside a highly experienced team that has a proven track record of building successful businesses. This is a unique opportunity to help shape a company at an early stage and grow into a future leader in an industry poised for global impact.\nWhat You Will Do\nDevelop and execute verification plans across the SoC/IP verification cycle, from architecture definition through tape-out and silicon bring-up\n\nBuild and maintain UVM/OVM-based verification environments for complex ASIC/SoC designs\n\nWrite and debug SystemVerilog testbenches, leveraging randomization, functional coverage, and assertion-based methodologies\n\nDrive root-cause analysis and debug of verification failures in close collaboration with design and architecture teams\n\nDefine and track coverage closure goals to ensure comprehensive verification sign-off\n\nPartner cross-functionally with design, architecture, and physical design teams to align verification strategy with tape-out schedules\n\nContribute to the evolution of verification methodology and infrastructure to support next-generation in-memory computing architectures\n\nWhat You Will Bring\nBS in Electrical Engineering, Computer Science, or a related field with 12+ years of industry experience (MS preferred with 7+ years)\n\nExperience across the full SoC/IP verification cycle - from architecture through tape-out and bring-up\n\nHands-on ASIC/SoC design verification test development and debug experience\n\nFluency with SystemVerilog (randomization, constraints, coverage, assertions) and verification methodologies such as UVM/OVM/VMM\n\nStrong problem-solving skills and a passion for tackling complex technical challenges, particularly in the AI domain\n\nPreferred Qualifications\nExperience with C/C++ and SystemC\n\nTrack record leading the creation and implementation of multiple SoC verification environments and driving tape-out efforts\n\nEqual Opportunity Employment Policy\nd-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.\nd-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. 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