{"id":377677,"url":"https://alion.io/job/d-matrix-sr-staff-pcb-design-engineer","title":"Sr. Staff PCB Design Engineer","company":{"id":8215,"name":"d-Matrix","domain":"d-matrix.ai","url":"https://alion.io/company/d-matrix","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Ashby","truth_index":{"grade":"A","score":85,"open_postings":5,"ghost_share":0,"stale_share":0.4,"repost_share":0,"time_to_fill_p50_days":83,"computed_at":"2026-11-01T06:10:25Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"staff","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":175000,"max":265000,"currency":"USD","period":"year","gross":null,"usd_annual":265000},"salary_estimate":null,"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Allegro","optional":false},{"name":"Python","optional":false}],"status":"live","first_seen_at":"2026-08-28T02:47:51Z","employer_posted_date":"2026-08-28","last_verified_at":"2026-11-01T13:50:00Z","board_verified":true,"closed_at":null,"days_open":65,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":65},"description":"At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration.\nWe value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together, we can help shape the endless possibilities of AI.\nRole Overview\nAs Sr. Staff PCB Design Engineer, you will lead the physical design of the boards that connect d-Matrix's AI silicon to the world. Our \"Corsair\" platforms push the limits of signal density and power delivery, and you will own layout for high-complexity, high-layer-count PCBAs (20+ layers) - ensuring 112G/224G SerDes signals stay clean and thousands of amps are delivered with minimal loss. Beyond hands-on layout, you will serve as custodian of our Design Methodology, driving the automation, tooling, and constraint management processes that let hardware development scale with precision and speed. You'll partner closely with power, ASIC, and manufacturing teams, and have the autonomy to build layout infrastructure from the ground up.\nWhat You Will Do\nLead full-cycle layout for high-complexity AI accelerator cards (PCIe form factors) and system baseboards\n\nArchitect and manage the Constraint Manager (CM) hierarchy in Cadence Allegro, defining the source of truth for high-speed routing rules and electrical constraints\n\nDevelop automation scripts (SKILL, Python, or TCL) to streamline layout tasks, DRC checks, and reporting\n\nExecute layout for ultra-high-speed interfaces including PCIe Gen5/6, CXL, and custom die-to-die (D2D) interconnects\n\nPartner with Power Engineers on PDN strategy, including multi-phase VRM layouts and decoupling capacitor placement for high-TDP ASICs\n\nDrive PCB stack-up definition, including advanced low-loss materials (e.g., Megtron 7/8) and hybrid build-ups\n\nServe as primary interface with fabricators and CMs to ensure DFM, DFT, and DFA requirements are met for high-yield production\n\nWhat You Will Bring\nBS in Electrical/Electronic Engineering or equivalent practical experience\n\n10+ years of experience in high-speed, high-density PCB layout for servers, networking, or AI accelerators\n\nProficiency in Cadence Allegro Constraint Manager, including T-junctions, differential pair phase-tuning, and Z-axis delay matching\n\nProven ability to write and deploy SKILL scripts or use Allegro's API to automate design audits and layout routines\n\nDeep understanding of high-speed routing techniques (back-drilling, via-in-pad, skip-vias) and HDI/ELIC design\n\nProven track record routing 112G SerDes and complex DDR5/HBM interfaces\n\nPreferred Qualifications\nExperience establishing a Library Management System and standardized footprint/padstack creation processes\n\nFamiliarity with PLM/PDM integration for managing layout releases and ECO workflows\n\nKnowledge of PCB warpage mitigation strategies for large-form-factor ASICs and MCMs\n\nEqual Opportunity Employment Policy\nd-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.\nd-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.","description_format":"text","description_chars":4254,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Electrical & Electronic Engineering","Processors, MCUs & AI Chips","AI Compute & Inference","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-09-05T21:21:40Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 2 · green card filings: 1","filings_12m":2,"filings_prev_12m":24,"green_card_filings_12m":1,"median_offered_wage_usd":184167,"route":null,"cap_exempt":false,"checked_at":"2026-10-29T16:27:21+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":0}],"liveness":{"score":52,"band":"ok","label":"Likely open","p_open":1,"p_active":0.868,"p_room":0.6,"age_days":65,"expected_fill_days":83,"reasons":["conf:0","velocity","win:late","crowd:"],"computed_at":"2026-11-01T06:10:25Z"},"pay":{"stated_usd_annual":265000,"is_top_pay":true},"html_url":"https://alion.io/job/d-matrix-sr-staff-pcb-design-engineer","json_url":"https://alion.io/job/d-matrix-sr-staff-pcb-design-engineer.json","meta":{"generated_at":"2026-11-01T17:52:50Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":27381,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-02T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":8215},"rest":"https://alion.io/mcp/rest/get_company?id=8215"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fd-matrix-sr-staff-pcb-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fd-matrix-sr-staff-pcb-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fd-matrix-sr-staff-pcb-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/d-matrix-sr-staff-pcb-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fd-matrix-sr-staff-pcb-design-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":377677}},{"tool":"search_jobs","arguments":{"company":"d-matrix.ai","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":377677},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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