{"id":63225,"url":"https://alion.io/job/d-matrix-staff-analog-design-engineer-txrx-datapath","title":"Staff Analog Design Engineer, TX/RX Datapath","company":{"id":8215,"name":"d-Matrix","domain":"d-matrix.ai","url":"https://alion.io/company/d-matrix","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Ashby","truth_index":{"grade":"A","score":88,"open_postings":7,"ghost_share":0,"stale_share":0.286,"repost_share":0,"time_to_fill_p50_days":83,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":155000,"max":250000,"currency":"USD","period":"year","gross":null,"usd_annual":250000},"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":false},{"name":"MATLAB","optional":false},{"name":"Python","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-08-19T03:58:20Z","employer_posted_date":"2026-08-19","last_verified_at":"2026-10-18T12:01:57Z","board_verified":true,"closed_at":null,"days_open":60,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":60},"description":"At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration.\nWe value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together, we can help shape the endless possibilities of AI.\nRole Overview\nYou will own the transmit and receive datapath of the high-speed SerDes on d-Matrix's IO chiplet - the interconnect that lets our inference accelerators scale beyond a single package. This is a hands-on, transistor-level design role on a small team, where you will personally carry blocks from specification through silicon characterization rather than handing specs off to someone else. The work spans porting proven datapath blocks to new process nodes and ground-up design of new blocks for our next-generation link, working closely with layout, package/signal-integrity, backend, and firmware engineers to bring your designs to working silicon.\nWhat You Will Do\nOwn transistor-level design of the SerDes transmit path: output drivers (SST and/or CML), pre-driver and serializer stages, and transmit-side FFE.\n\nOwn transistor-level design of the receive front-end: termination and ESD-aware input network, CTLE, VGA, samplers, and where applicable ADC-based front-ends.\n\nDesign and verify the equalization path - DFE and FFE architecture, tap resolution, and adaptation behavior - and own the trade study behind the architecture you choose.\n\nDerive block-level specifications from link budgets covering insertion loss, crosstalk, reflection, jitter, and BER targets, and defend those specifications in design review.\n\nBuild the verification environment for your blocks - testbenches, PVT corner coverage, six-sigma Monte Carlo, transient noise, and post-layout back-annotated simulation - and provide behavioral and Verilog-A models for full-chip verification, supporting backend engineers through integration.\n\nPerform link and channel modeling in MATLAB, Python, or equivalent - S-parameter channel and package models, statistical eye and BER analysis, and equalization trade studies.\n\nDrive layout of your blocks in deep sub-micron nodes, working with layout engineers on floorplan, matching, shielding, current density, and parasitic control, and co-designing with package/signal-integrity engineers on bump maps, escape routing, and channel budgets.\n\nContribute to testboard design, then take your blocks through silicon bring-up and bench characterization, correlating measured performance against simulation.\n\nWhat You Will Bring\nBS/MS/PhD in Electrical Engineering, with 8+ years of hands-on analog and mixed-signal circuit design experience.\n\nDemonstrated ownership of a SerDes transmit or receive datapath block through to working silicon in a high-speed link.\n\nDeep knowledge of high-speed driver design, receive front-end design, and equalization, with practical familiarity with the adjacent clocking and CDR blocks your datapath interfaces with.\n\nPractical command of jitter and noise analysis - decomposition, budgeting, and the simulation methodology to quantify each contributor.\n\nCircuit design experience in advanced FinFET or GAA process nodes, with hands-on use of industry-standard analog design and simulation tools and methodologies (e.g., Cadence Virtuoso, Spectre, Monte Carlo/corner analysis, post-layout simulation) and link/channel modeling (e.g., MATLAB, Python, S-parameter models).\n\nSilicon bring-up and bench debug experience with high-speed lab equipment such as scopes and BERTs, with the judgment to distinguish a design problem from a measurement problem.\n\nPreferred\nDie-to-die interconnect experience - UCIe, BoW, or a proprietary D2D PHY - including the specific constraints of short-reach, low-energy-per-bit links.\n\nPAM4 signaling and DSP-based receiver architectures, including ADC-based front-ends.\n\nFamiliarity with relevant specifications: UCIe, OIF CEI-112G/224G, IEEE 802.3, PCIe Gen6/Gen7.\n\nExperience porting a datapath block across process nodes, with a realistic sense of what that effort actually costs.\n\nIBIS-AMI model generation, or SerDes ATE and production test development.\n\nParticipation in or contribution to standards bodies.\n\nEqual Opportunity Employment Policy\nd-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.\nd-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.","description_format":"text","description_chars":5574,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","AI Compute & Inference","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-08-19T03:58:20Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 2 · green card filings: 1","filings_12m":2,"filings_prev_12m":24,"green_card_filings_12m":1,"median_offered_wage_usd":184167,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":1}],"liveness":{"score":66,"band":"ok","label":"Likely open","p_open":1,"p_active":0.877,"p_room":0.75,"age_days":59,"expected_fill_days":83,"reasons":["conf:3","velocity","win:late"],"computed_at":"2026-10-17T05:46:00Z"},"pay":{"stated_usd_annual":250000,"is_top_pay":true},"html_url":"https://alion.io/job/d-matrix-staff-analog-design-engineer-txrx-datapath","json_url":"https://alion.io/job/d-matrix-staff-analog-design-engineer-txrx-datapath.json","meta":{"generated_at":"2026-10-18T13:49:35Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":20530,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-19T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":8215},"rest":"https://alion.io/mcp/rest/get_company?id=8215"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fd-matrix-staff-analog-design-engineer-txrx-datapath"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fd-matrix-staff-analog-design-engineer-txrx-datapath"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fd-matrix-staff-analog-design-engineer-txrx-datapath"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/d-matrix-staff-analog-design-engineer-txrx-datapath\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fd-matrix-staff-analog-design-engineer-txrx-datapath"}]}