{"id":768343,"url":"https://alion.io/job/delosdata-physical-design-engineer","title":"Physical Design Engineer","company":{"id":673877,"name":"Delos Data","domain":"delosdata.com","url":"https://alion.io/company/delosdata","size_band":null,"is_staffing_agency":false,"is_intermediary":false,"ats_vendor":"Ashby","truth_index":null},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"hiring_geo_confidence":"structured","locations":["Palo Alto, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":180000,"max":260000,"currency":"USD","period":"year","gross":null,"usd_annual":260000},"salary_estimate":null,"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false}],"status":"live","first_seen_at":"2026-09-10T21:32:04Z","employer_posted_date":"2026-09-10","last_verified_at":"2026-09-24T09:02:01Z","board_verified":true,"closed_at":null,"days_open":13,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":13},"description":"We are a startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors.\nThe company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver.\nHeadquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously.\nWhat We Need:\nWe are looking for a Principal Physical Design Engineer to serve as an early member of our physical design team.\nYou will own some of the most challenging physical implementation problems in the design, drive critical blocks and top-level integration, and help establish the methodologies required to achieve performance, power, area, and schedule targets.\nThis is a deeply hands-on role for an engineer who can independently take complex designs from floorplan through signoff, solve difficult timing and implementation problems, and provide technical leadership across the broader physical design team.\nKey Responsibilities:\nOwn physical implementation of complex blocks and subsystems from synthesized netlist through signoff.\n\nDevelop floorplans considering hierarchy, macros, interfaces, congestion, timing, power, and routability.\n\nDevelop and optimize power-grid implementations and support IR-drop and electromigration closure.\n\nDrive placement, optimization, clock-tree synthesis, routing, extraction, timing closure, and ECO implementation.\n\nOwn difficult setup, hold, signal-integrity, congestion, and physical implementation problems.\n\nLead timing closure across block boundaries and support top-level timing convergence.\n\nPerform and drive static timing analysis across multiple modes and corners.\n\nSupport signal-integrity analysis and timing impact from crosstalk, variation, and physical effects.\n\nDrive physical signoff, including DRC, LVS, antenna, density, connectivity, and related physical verification requirements.\n\nPerform or support power integrity analysis, including static and dynamic IR drop and electromigration.\n\nDevelop implementation strategies for high-performance and physically challenging portions of the design.\n\nPartner with RTL and architecture teams to identify implementation problems early and recommend architectural or logical changes where appropriate.\n\nWork closely with DFT, verification, package, SI/PI, and other engineering teams to resolve cross-functional design issues.\n\nDevelop and improve physical design flows, scripts, automation, metrics, and methodologies.\n\nEvaluate implementation results and identify opportunities to improve PPA, runtime, convergence, and design quality.\n\nProvide technical guidance and mentorship to other physical design engineers.\n\nParticipate in design reviews, methodology reviews, and tapeout readiness assessments.\n\nServe as a technical escalation point for complex physical design and signoff issues.\n\nRequired Skills and Qualifications:\n10+ years of ASIC or SoC physical design experience with multiple successful tapeouts.\n\nExpert-level understanding of floorplanning, placement, CTS, routing, optimization, timing closure, ECOs, and physical verification.\n\nStrong expertise in static timing analysis and multi-mode, multi-corner timing closure.\n\nStrong understanding of power delivery, IR drop, electromigration, and signal integrity.\n\nDemonstrated ability to independently own complex blocks or major portions of a chip through signoff.\n\nStrong understanding of clock design, timing constraints, variation, extraction, and advanced-node physical effects.\n\nExperience with industry-standard Cadence and/or Synopsys physical implementation and signoff tools.\n\nStrong scripting and automation skills using Tcl, Python, Perl, or similar languages.\n\nAbility to debug complex design problems across RTL, timing, physical implementation, and signoff domains.\n\nStrong communication skills and ability to provide technical leadership without requiring formal management authority.\n\nDesired Skills:\nExperience with advanced process nodes.\n\nExperience with large, high-frequency or highly interconnected semiconductor designs.\n\nExperience with hierarchical design and top-level physical integration.\n\nExperience developing physical design methodologies and automation.\n\nExperience working closely with package, SI/PI, and power-delivery teams.\n\nExperience with multi-die, chiplet, or advanced packaging architectures.\n\nFamiliarity with EDA tool evaluation, benchmarking, and optimization.\n\nExperience in an early-stage semiconductor environment.\n\nAdditional Requirements:\nAbility to independently drive complex technical problems to closure.\n\nComfortable operating across both detailed implementation work and broader chip-level design considerations.\n\nAbility to work effectively in a highly collaborative, fast-paced engineering organization.\n\nCompensation:\nTarget base salary for this role is $180,000 - $260,000 per year, plus meaningful equity, benefits, and 401(k). Salary ranges are determined by role, level, experience, and location.\nWe are an equal opportunity employer. We value a range of perspectives and experiences and make employment decisions based on merit and business needs. We do not discriminate on the basis of legally protected characteristics.\nAgency Note:\nWe do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired.","description_format":"text","description_chars":6065,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":["Equity"],"hiring_locations":[{"name":"Canada","iso":"CA","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Artificial Intelligence","AI Agents"],"lifecycle":[{"event":"open","at":"2026-09-11T20:42:10Z"}],"liveness":{"score":64,"band":"ok","label":"Likely open","p_open":1,"p_active":0.716,"p_room":0.9,"age_days":13,"expected_fill_days":23,"reasons":["conf:3","win:mid"],"computed_at":"2026-09-24T05:45:00Z"},"pay":{"stated_usd_annual":260000,"is_top_pay":true},"html_url":"https://alion.io/job/delosdata-physical-design-engineer","json_url":"https://alion.io/job/delosdata-physical-design-engineer.json","meta":{"generated_at":"2026-09-24T09:31:43Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers"}}