{"id":833674,"url":"https://alion.io/job/dolphin-semiconductor-verification-engineer-wm","title":"Verification Engineer (W/M)","company":{"id":53652,"name":"Dolphin Semiconductor","domain":"dolphin-semiconductor.com","url":"https://alion.io/company/dolphin-semiconductor","size_band":"51-200","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Schema","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"contractor","work_mode":"remote","remote_scope":"stated_countries","remote_scope_basis":"posting_text","remote_working_hours":{"label":"CET","utc_offset_min":1,"utc_offset_max":1},"hiring_geo_confidence":"explicit","locations":[],"countries":[],"hiring_countries":["FR"],"hiring_countries_total":1,"salary":null,"salary_estimate":{"min_usd":54000,"max_usd":99000,"period":"year","method":"role_seniority_country_cell","sample_n":16},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence JasperGold","optional":false},{"name":"Formal Verification","optional":false},{"name":"HPC","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"Windows","optional":false},{"name":"Git","optional":true}],"status":"live","first_seen_at":"2026-09-11T14:02:47Z","employer_posted_date":"2026-09-11","last_verified_at":"2026-11-01T14:43:59Z","board_verified":true,"closed_at":null,"days_open":51,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":51},"description":"To support the growth of our Power Management business and meet our customers' needs around density, power consumption, and operating frequency for their integrated circuits, we are looking for an IP Verification Engineer (W/M), based in Meylan, France.\nAs part of our verification team, you will work 100% on functional verification of products designed to optimize the energy efficiency of our customers' circuits, across fields such as Edge-IoT, automotive, and high-performance computing (HPC).\nWorking closely with senior verification engineers, tech leads, and designers, you will help build effective verification strategies that cut down validation time while maximizing coverage, in order to hit the performance and power targets of products such as the Maestro Power Manager Unit (PMU) and the Meerkat distributed margin sensor.\nFor IPs aimed at the automotive market, you will help verify ISO 26262 requirements and assess how robust blocks are against permanent and transient faults. This role will let you gradually grow your scope - from UVM simulation into fault injection and formal verification.\nYour missions\nFunctional verification (UVM)\nHelp define the verification plan (coverage-driven methodology) from product specifications, and track it through to closure on your scope\n\nBuild and debug UVM verification environments: agents, sequences, virtual sequencer, scoreboards, reference models, RAL (uvm_reg), factory, callbacks, hierarchical configuration\n\nBuild reusable, parameterized testbenches (SystemVerilog) that are portable across different IP configurations\n\nWrite directed and constrained-random stimuli, making use of constrained randomization\n\nBuild checkers and SVA assertions, along with the bind strategy behind them\n\nDebug gaps between spec and RTL, and support the design team on your scope\n\nIntegrate and configure protocol VIP s, or build UVM agents yourself when the IP calls for it\n\nBuild protocol compliance checkers, end-to-end scoreboards, and dedicated protocol coverage (transactions, back-to-back cases, edge cases, error handling, arbitration)\n\nFunctional safety and fault injection (ISO 26262)\nHelp verify safety requirements and justify the hardware metrics (SPFM, LFM, PMHF)\n\nBuild and run fault injection campaigns (stuck-at for permanent faults, SEU/SET for transient faults): instrument the testbench, select and propagate faults, define detectors and observables\n\nAnalyze fault campaign results, help classify faults (detected, undetected, safe, residual), and feed that into the FMEDA analysis\n\nFlag improvement opportunities on safety mechanisms back to the design team\n\nBuild up your skills on fault simulation and formal safety verification (FSV) tools, to cut down the effort needed to qualify unclassified faults\n\nCouverture\nImplement the functional coverage strategy: covergroups, coverpoints, crosses, bins, and transitions derived from the verification plan, including for parameterized IPs\n\nAnalyze code coverage (line, branch, condition, expression, toggle, FSM)\n\nInvestigate coverage gaps, justify and document exclusions, and log waivers in the refinement files with supporting justification\n\nUse coverage and regression management tools, and help drive coverage closure to sign-off criteria\n\nFormal verification\nWrite SVA properties and environment constraints (assumes), and build strategies to reach convergence\n\nRun the relevant formal apps: property checking (FPV), connectivity check, register map check, X-propagation, deadlock detection, feasibility analysis to justify coverage waivers\n\nAnalyze and debug counterexamples, and assess formal completeness (proof core, formal coverage)\n\nWork with Questa Formal and JasperGold\n\nMethodology and project execution\nKeep up with the latest verification techniques, tools, and technologies\n\nHelp continuously improve and maintain the verification methodology and flow\n\nContribute to workload estimates and progress tracking on your activities\n\nWork closely with tech leads, project managers, designers, and other team members\n\nYou're about to become a Dolphin...\nYou have an engineering degree or a Master's degree (Bac+5) and at least 5 years of experience in functional verification of digital circuits.\nYou're technically curious, rigorous in how you analyze problems, and you enjoy digging into a good debug.\nMust-have skills and experience:\nStrong command of UVM methodology, with solid prior experience on a complete verification environment\n\nStrong command of SystemVerilog for verification (classes, constraints, interfaces, SVA assertions), and the ability to read and understand RTL (Verilog / SystemVerilog / VHDL)\n\nHands-on experience with functional coverage and code coverage techniques, and a good understanding of coverage closure (gap analysis, waivers)\n\nExperience verifying at least one standard communication protocol (APB/AHB/AXI, I2C/SPI/I3C, or equivalent)\n\nGood scripting skills (Tcl, Shell, Python, Perl...) for automating verification flows and regressions\n\nComfortable working in both Linux and Windows environments\n\nHands-on experience with EDA simulation, coverage, and debug tools (Cadence, Siemens EDA, Synopsys)\n\nPreferred skills and experience:\nSome exposure to ISO 26262 functional safety verification and fault injection campaigns\n\nPrior experience in formal verification (Questa Formal, JasperGold, or equivalent)\n\nFamiliarity with SVN and Git\n\nBenefits of becoming a Dolphin:\nJoin a small-to-medium-sized company backed by the JOLT investment fund.\n\nCompensation package: fixed salary (based on experience), profit-sharing, meal vouchers, health insurance and provident plan.\n\nLocated in a \"green zone for intellectual capital,\" our company is committed to sustainable mobility, with a strong emphasis on cycling. Through our Sustainable Mobility Fund, we offer: €0.12/km for carpooling, €0.25/km for cycling, reimbursement of 60% for transport subscriptions and bike rentals, and a €300 subsidy for purchasing a bike after one year of service. We also provide well-equipped facilities: secure bike parking, showers, as well as workshops and cycling activities throughout the year.\n\nExecutive status, annual hours package, 10 RTT (redundant days off), CET (compte épargne-temps).\n\nWork-from-home agreement for 20 days per year or the possibility of regular or full remote work depending on personal constraints.\n\nAnd of course, the Welcome pack when you join!!\n\nIs this role not an exact fit? Sign up to stay in touch, we’ll let you know when we have new positions on the team.\nDon't wait any longer, take the plunge!","description_format":"text","description_chars":6572,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":["Health insurance"],"hiring_locations":[{"name":"France","iso":"FR","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-12T17:44:20Z"}],"visa":[],"liveness":{"score":32,"band":"fade","label":"Fading","p_open":1,"p_active":0.581,"p_room":0.55,"age_days":50,"expected_fill_days":35,"reasons":["conf:1","win:tail"],"computed_at":"2026-11-01T06:10:25Z"},"pay":null,"html_url":"https://alion.io/job/dolphin-semiconductor-verification-engineer-wm","json_url":"https://alion.io/job/dolphin-semiconductor-verification-engineer-wm.json","meta":{"generated_at":"2026-11-01T18:20:17Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":28126,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-02T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":53652},"rest":"https://alion.io/mcp/rest/get_company?id=53652"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fdolphin-semiconductor-verification-engineer-wm"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fdolphin-semiconductor-verification-engineer-wm"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fdolphin-semiconductor-verification-engineer-wm"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/dolphin-semiconductor-verification-engineer-wm\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fdolphin-semiconductor-verification-engineer-wm"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":833674}},{"tool":"search_jobs","arguments":{"company":"dolphin-semiconductor.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":833674},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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