{"id":663137,"url":"https://alion.io/job/drw-senior-fpga-engineer","title":"Senior FPGA Engineer","company":{"id":58537,"name":"DRW","domain":"drw.com","url":"https://alion.io/company/drw","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"B","score":83,"open_postings":55,"ghost_share":0,"stale_share":0.473,"repost_share":0,"time_to_fill_p50_days":73,"computed_at":"2026-09-28T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Tel Aviv, Israel"],"countries":["IL"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":120000,"max_usd":276000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1198},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2024-04-03T14:17:56Z","employer_posted_date":"2026-09-15","last_verified_at":"2026-09-29T01:27:24Z","board_verified":true,"closed_at":null,"days_open":908,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":907},"description":"DRW is a diversified trading firm with over 3 decades of experience bringing sophisticated technology and exceptional people together to operate in markets around the world. We value autonomy and the ability to quickly pivot to capture opportunities, so we operate using our own capital and trading at our own risk. \nHeadquartered in Chicago with offices throughout the U.S., Canada, Europe, and Asia, we trade a variety of asset classes including Fixed Income, ETFs, Equities, FX, Commodities and Energy across all major global markets. We have also leveraged our expertise and technology to expand into three non-traditional strategies: real estate, venture capital and cryptoassets. \nWe operate with respect, curiosity and open minds. The people who thrive here share our belief that it’s not just what we do that matters-it's how we do it. DRW is a place of high expectations, integrity, innovation and a willingness to challenge consensus. \nWe are currently seeking a Senior FPGA Enginee r to join one of our trading teams. While DRW has been leveraging FPGA technology for a number of years, you will have the opportunity to build an FPGA application from scratch for an existing team. We’re seeking a candidate that has a strong understanding of software and hardware interaction. This person will participate in the full development lifecycle, including system and block level testing, of low latency high throughput FPGA design.\nResponsibilities: \nArchitect and implement new FPGA applications (synthesis, place & route, static timing analysis, documentation) from the ground up\nResearch and evaluate a variety of cutting-edge FPGA hardware and technologies\nPropose creative solutions to overcome FPGA/hardware limitations\nLiaise directly with software and other design teams\nConduct lab debugging and characterization of new hardware\nCandidate Requirements:\nBachelor's degree or higher, Computer/Electrical Engineering graduated with honors from a leading university, with 3+ years of experience within the field; (Master's degree or higher also counts for experience)\nSolid Hardware Engineering experience, especially with FPGA\nHighly autonomous with a can-do attitude able to lead an FPGA based project from system requirements to production\nStrong capacity to quickly evaluate FPGA based project feasibility based on hardware limitation\nStrong skills in RTL logic design and verification; 2+ years of experience writing Verilog or SystemVerilog\nStrong knowledge of FPGAs fabric\nExperience in FPGA design flow including synthesis, place & route, static timing analysis is required\nKnowledge of Ethernet and Gigabit high speed serial interfaces\nStrong working knowledge of either XILINX or ALTERA FPGA design flow\nExperience with Python verification framework is a plus\nExcellent research and data gathering skills\nFor more information about DRW's processing activities and our use of job applicants' data, please view our Privacy Notice athttps://drw.com/privacy-notice.\nCalifornia residents, please review the California Privacy Notice for information about certain legal rights at https://drw.com/california-privacy-notice .","description_format":"text","description_chars":3138,"description_truncated":false,"requirements":{"experience_years_min":3,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Hedge Funds & Alternative Investments"],"lifecycle":[{"event":"open","at":"2026-09-10T21:43:25Z"}],"liveness":{"score":7,"band":"cold","label":"Long shot","p_open":1,"p_active":0.255,"p_room":0.28,"age_days":907,"expected_fill_days":73,"reasons":["conf:1","velocity","win:tail","crowd:brand"],"computed_at":"2026-09-28T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/drw-senior-fpga-engineer","json_url":"https://alion.io/job/drw-senior-fpga-engineer.json","meta":{"generated_at":"2026-09-29T01:47:18Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":1468,"day_limit":5000,"remaining_today":3532,"minute_limit":60,"resets_at":"2026-09-30T00:00:00Z"}}}