{"id":2389914,"url":"https://alion.io/job/edgecortix-india-senior-pcie-verification-engineer","title":"[India] Senior PCIe Verification Engineer","company":{"id":48043,"name":"EdgeCortix","domain":"edgecortix.com","url":"https://alion.io/company/edgecortix","size_band":"51-200","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"BambooHR","truth_index":{"grade":"D","score":53,"open_postings":19,"ghost_share":0.789,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-30T05:48:23Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"explicit","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":17000,"max_usd":45000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":18},"experience_years_min":6,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Computer Vision","optional":false},{"name":"Machine Learning","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-07-16T00:00:00Z","employer_posted_date":"2026-07-16","last_verified_at":"2026-10-30T11:50:50Z","board_verified":true,"closed_at":null,"days_open":106,"trust":{"level":"ghost","repost_count":0,"flags":["stale","company_stale"],"days_open":105},"description":"Introduction\nWe are seeking an experienced Senior PCIe Verification Engineerto join our SoC Verification team. The ideal candidate should have strong expertise in PCI Express (PCIe) IP/Subsystem verification using SystemVerilog/UVM and hands-on experience in 2-3 successful SoC tape-outs. The candidate will be responsible for developing robust verification environments, driving verification closure, and ensuring first-pass silicon success for PCIe-based subsystems.\nAbout Edgecortix\nAt Edgecortix we are a deep-tech startup revolutionizing edge computing with artificial intelligence and novel high efficiency silicon on chip design. Originating from multiple years of research, our unique AI hardware & software co-design principle and the Dynamic Neural Accelerator ® AI processor IP are geared towards positively disrupting the rapidly growing artificial intelligence edge hardware space and bring the power of AI and machine learning to all kinds of devices. Our operations are headquartered in Tokyo, Japan, with offices in Singapore, Virginia, California in the US. In addition, we are starting a new Design Center in India, located in Hyderabad.\nThe Team\nAs an engineering driven company we are working to define and solve the hardest problems in AI including computer vision, speech, and natural language, geared towards real-time capabilities on small to medium form factor devices. We originated out of multiple years of research, as such at our core we value learning, intellectual curiosity, and self-starters. We have the ambitious goal of enabling cloud-level performance with significantly better energy-efficiency for AI inference at the edge.\nYour Role and Responsibilities:\nDevelop and execute comprehensive verification plans for PCIe IPs, subsystems, and SoC integration.\nBuild reusable SystemVerilog/UVM verification environments from scratch.\nDevelop constrained-random and directed test scenarios for PCIe verification.\nVerify PCIe functionality across LTSSM, Link Training, Configuration Space, Enumeration, Data Link Layer, Transaction Layer, and PHY interactions.\nVerify advanced PCIe features such as MSI/MSI-X, AER, ASPM, LTR, SR-IOV, ATS, PASID, FLR, and Power Management (as applicable).\nPerform protocol compliance verification using industry-standard PCIe VIPs .\nDevelop functional coverage models, assertions, scoreboards, monitors, and protocol checkers.\nAnalyze code coverage and functional coverage and drive verification closure.\nPerform RTL, protocol, and UVM testbench debugging.\nSupport gate-level simulations, regression execution, and post-silicon bring-up activities when required.\nCollaborate closely with RTL, architecture, firmware, physical design, DFT, and validation teams throughout the SoC development cycle.\nDesired Qualifications:\n6-12 years of experience in functional verification using SystemVerilog and UVM.\nStrong expertise in PCI Express (PCIe Gen4/Gen5/Gen6) verification.\nHands-on experience with PCIe Verification IP (VIP).\nSolid understanding of PCIe architecture and protocol layers:Physical Layer\nData Link Layer\nTransaction Layer\nConfiguration Space\nLTSSM\nError Handling and Recovery\nExperience verifying DMA-based PCIe designs and AXI-to-PCIe bridge architectures.\nStrong knowledge of AXI4 protocol and SoC interconnects.\nExperience writing SystemVerilog Assertions (SVA).\nStrong experience in constrained-random, assertion-based, and coverage-driven verification.\nExperience with gate-level simulations and timing-aware verification.\nExcellent RTL and protocol debugging skills.\nSoC Experience\nHands-on experience with 2-3 successful SoC tape-outs.\nExperience verifying PCIe integration at the SoC level.\nExposure to SoC boot flows, reset sequences, clocking architecture, interrupt handling, and subsystem integration.\nExperience working with firmware and software teams during integration and bring-up.\n\nWhat’s in it for you?\nMake a difference: you will have the opportunity to join a well-funded fabless AI semiconductor startup that is disrupting the AI software and hardware co-design space. Be an integral part of its growth and momentum.\nBenefits and Perks\nHighly competitive salary and stock options\nFlex work time\nTop-tier employee benefits","description_format":"text","description_chars":4220,"description_truncated":false,"requirements":{"experience_years_min":6,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":["Stock options"],"hiring_locations":[{"name":"India","iso":"IN","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Edge AI","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-12T20:56:16Z"}],"visa":[],"liveness":{"score":8,"band":"cold","label":"Long shot","p_open":1,"p_active":0.282,"p_room":0.28,"age_days":106,"expected_fill_days":36,"reasons":["conf:4","stale_co","ghost","win:tail","crowd:"],"computed_at":"2026-10-30T05:48:23Z"},"pay":null,"html_url":"https://alion.io/job/edgecortix-india-senior-pcie-verification-engineer","json_url":"https://alion.io/job/edgecortix-india-senior-pcie-verification-engineer.json","meta":{"generated_at":"2026-10-30T16:39:30Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":4847,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-31T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":48043},"rest":"https://alion.io/mcp/rest/get_company?id=48043"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fedgecortix-india-senior-pcie-verification-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fedgecortix-india-senior-pcie-verification-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fedgecortix-india-senior-pcie-verification-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/edgecortix-india-senior-pcie-verification-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fedgecortix-india-senior-pcie-verification-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":2389914}},{"tool":"search_jobs","arguments":{"company":"edgecortix.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":2389914},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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