{"id":2389870,"url":"https://alion.io/job/edgecortix-japan-accelerator-ip-design-engineer-asic-rtl","title":"[Japan] Accelerator IP Design Engineer (ASIC, RTL)","company":{"id":48043,"name":"EdgeCortix","domain":"edgecortix.com","url":"https://alion.io/company/edgecortix","size_band":"51-200","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"BambooHR","truth_index":{"grade":"D","score":53,"open_postings":19,"ghost_share":0.789,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-21T05:46:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"explicit","locations":["Kawasaki, Japan"],"countries":["JP"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"CI/CD","optional":false},{"name":"Computer Vision","optional":false},{"name":"Machine Learning","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"C++","optional":true},{"name":"Java","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2025-01-27T00:00:00Z","employer_posted_date":"2025-01-27","last_verified_at":"2026-10-21T07:24:22Z","board_verified":true,"closed_at":null,"days_open":632,"trust":{"level":"ghost","repost_count":0,"flags":["stale","company_stale"],"days_open":632},"description":"Introduction\nEdgecortix Inc. is seeking a Hardware Design Engineer with proven RTL/logic and ASIC design expertise. If you have a strong desire to build state-of-the-art digital chips and systems join us and let's reshape the future of AI.\nAbout Edgecortix\nAt Edgecortix we are a deep-tech startup revolutionizing edge computing with artificial intelligence and novel high efficiency silicon on chip design. Originating from multiple years of research, our unique AI hardware & software co-design principle and the Dynamic Neural Accelerator ® AI processor IP are geared towards positively disrupting the rapidly growing artificial intelligence edge hardware space and bring the power of AI and machine learning to all kinds of devices. Our operations are headquartered in Tokyo, Japan, with offices in Singapore, Virginia, California in the US. In addition, we are starting a new Design Center in India, located in Hyderabad.\nThe Team\nAs an engineering driven company we are working to define and solve the hardest problems in AI including computer vision, speech, and natural language, geared towards real-time capabilities on small to medium form factor devices. We originated out of multiple years of research, as such at our core we value learning, intellectual curiosity, and self-starters. We have the ambitious goal of enabling cloud-level performance with significantly better energy-efficiency for AI inference at the edge.\nYour Role and Responsibilities:\nIdeal candidates will have expertise in several of the following areas:\nRTL Design and module-level verification of modules for Edgecortix inference accelerator IP.\nParticipate in synthesis, STA, and power estimation activities.\nPropose and implement low-level micro-architectural optimizations for better area, power, and placeability/routability of design targeting specific tech processes, power, and area budgets.\nWork closely with our architects to support architectural-level decisions providing expert feedback to ensure high design scalability.\nCollaborate with our architects and compiler engineers to determine the best way of implementing new functionality and defining architectural specs.\nEngage in system integration activities for SoC design using third-party IPs and integration tools.\nEngage in IP-level and system-level verification and debugging activities using SystemVerilog and UVM.\nEmbrace high standards of engineering practices such as code reviews, technical documentation, propper testing process, continuous integration, and release engineering.\nDesired Qualifications (ASIC)\nAbility to write clean, readable, synthesizable RTL.\nFamiliarity with AXI, Avalon or similar protocol.\nExperience in low power RTL design.\nExperience in performing logic synthesis using Cadence or Synopsys tools.\nExperience in writing timing constraints and power intent definitions.\nExperience in optimizing design for timing.\nExperience in using power analysis tools such as Joules or PowerPro.\nUnderstanding of Physical Design issues.\nUnderstanding of using fixed-point arithmetic for approximating floating-point computations.\nExperience with verification using SystemVerilog and UVM.\nExperience with DDR, PCI-E, MIPI CSI or other high speed protocols is a plus.\nDecent scripting and automation skills using TCL, Python, and Make.\nBasic programming skills in statically typed languages such as C++ or Java.\nWhat’s in it for you?\nMake a difference: you will have the opportunity to join a well-funded fabless AI semiconductor startup that is disrupting the AI software and hardware co-design space. Be an integral part of its growth and momentum.\nBenefits and Perks\n· Highly competitive salary and stock options\n· Flex work time and ability to work fully remotely\n· Support for obtaining visa and relocation support (in case of non-remote)","description_format":"text","description_chars":3812,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":["Stock options"],"hiring_locations":[{"name":"Japan","iso":"JP","kind":"country"}],"hiring_excludes":[],"relocation_offered":true,"industries":["Angel Networks & Startup Accelerators","Processors, MCUs & AI Chips","Edge AI","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-12T20:56:16Z"}],"visa":[],"liveness":{"score":4,"band":"cold","label":"Long shot","p_open":1,"p_active":0.134,"p_room":0.28,"age_days":632,"expected_fill_days":32,"reasons":["conf:2","stale_co","ghost","win:tail","crowd:"],"computed_at":"2026-10-21T05:46:15Z"},"pay":null,"html_url":"https://alion.io/job/edgecortix-japan-accelerator-ip-design-engineer-asic-rtl","json_url":"https://alion.io/job/edgecortix-japan-accelerator-ip-design-engineer-asic-rtl.json","meta":{"generated_at":"2026-10-21T17:09:47Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":24174,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-22T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":48043},"rest":"https://alion.io/mcp/rest/get_company?id=48043"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fedgecortix-japan-accelerator-ip-design-engineer-asic-rtl"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fedgecortix-japan-accelerator-ip-design-engineer-asic-rtl"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fedgecortix-japan-accelerator-ip-design-engineer-asic-rtl"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/edgecortix-japan-accelerator-ip-design-engineer-asic-rtl\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fedgecortix-japan-accelerator-ip-design-engineer-asic-rtl"}]}