{"id":2573237,"url":"https://alion.io/job/efficient-computer-senior-rtl-design-engineer","title":"Senior RTL Design Engineer","company":{"id":2217001,"name":"Efficient Computer","domain":"efficient.computer","url":"https://alion.io/company/efficient-computer","size_band":"11-50","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"B","score":75,"open_postings":5,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-15T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Francisco, United States","Austin, United States","Pittsburgh, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":180000,"max":245000,"currency":"USD","period":"year","gross":null,"usd_annual":245000},"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false}],"status":"live","first_seen_at":"2026-10-14T21:12:39Z","employer_posted_date":"2026-10-14","last_verified_at":"2026-10-15T11:26:10Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Efficient Computer is rethinking computing from the ground up to solve one of AI's biggest challenges: energy. Our Fabric architecture delivers a 10-100x improvement in energy efficiency for general-purpose computation, including AI, while supporting familiar programming languages and software frameworks-unlocking new possibilities for autonomous machines, intelligent infrastructure, wearables, and space systems. With our first processor, Electron E1, now shipping in volume and more than $97 million in Series B financing recently announced, we're accelerating customer deployments and scaling our architecture to data center performance. Join us to build the hardware and software that bring intelligence wherever it's needed and help shape the next generation of computing.\nWe are looking for a Senior Design Engineer to design, integrate, and sign off RTL for blocks across our power-efficient SoC: the compute fabric's on-chip interconnect and memory interfaces, low-power and always-on logic, and standard peripheral IP (RISC-V, NVM, I2S, I2C). As a hands-on individual contributor, you will take blocks from microarchitecture spec through clean, synthesis-ready RTL, working closely with architects, the design lead, DV, physical design, and firmware to tape out an industry-leading ultra-low-power SoC.\nThis is a unique opportunity to join a growing HW engineering org early and leave your mark on our products and processes as we move from initial product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!\nKey Responsibilities\nRTL Design & Integration\nImplement microarchitecture and RTL for assigned blocks in the compute fabric, on-chip networks/NoC, memory interfaces, and peripheral subsystems, working from architecture and uArch specifications.\nIntegrate third-party and in-house IP (RISC-V cores, NVM controllers, SRAM wrappers, I2S/I2C/APB peripherals) at the subsystem and SoC level, including bus fabric hookup and memory-mapped register interfaces.\nWrite and maintain uArch and design documentation for your blocks; present them in design reviews with architecture, DV, and physical design.\nFront-End Design Flows & Sign-off\nOwn block-level front-end quality: lint-clean RTL, CDC and RDC analysis with waivers reviewed and documented, and LEC between RTL and netlist.\nRun synthesis, write and maintain SDC timing constraints, and analyze STA reports; iterate on RTL to meet timing, area, and power targets.\nDrive issues to closure with physical design during timing and congestion closure.\nLow-Power Design\nImplement low-power RTL per UPF intent: power domains, isolation, level shifters, retention, and fine-grained clock gating.\nContribute to PMU and always-on (AON) logic, such as power sequencing state machines and wakeup event aggregation.\nEnsure clock-gating enables are timing-clean and CDC-correct; run RTL power analysis and act on the results.\nVerification Support & Debug\nRun block-level simulations and debug failures alongside the DV team; contribute directed test scenarios for corner cases, back-pressure, and power-state transitions.\nRun and debug gate-level simulations.\nSupport silicon bring-up with RTL-level debug during lab validation.\nRequired Qualifications & Experience\n8-10 years of front-end digital design experience on processor, accelerator, or SoC products.\nSignificant contributions to at least two tapeout cycles.\nStrong proficiency in SystemVerilog for synthesizable RTL: state machines, arbiters, FIFOs and flow control, and datapath logic.\nHands-on experience with standard VLSI front-end flows: lint, CDC/RDC, LEC, synthesis, SDC constraints, and STA, with the ability to interpret and act on their reports.\nExperience with low-power RTL techniques: UPF-driven flows, clock gating, power domains, isolation, and retention.\nWorking knowledge of at least one on-chip bus protocol (AXI, AHB, APB, TileLink, or NoC equivalent) at the RTL level.\nExperience with on-chip memories: SRAM wrappers, banking, and memory-mapped register interfaces.\nComfortable running RTL simulations and debugging with waveform tools.\nClear written and verbal communication; able to document designs and hold design reviews.\nDesired Qualifications & Experience\nExperience designing or integrating on-chip networks, dataflow pipelines, or memory subsystems.\nFamiliarity with NVM controller RTL (MRAM, RRAM, etc.), including ECC and program/erase sequencing.\nExperience with very low power design techniques and the RTL design choices they require.\nUnderstanding of parallel execution models such as dataflow, SIMD, or systolic arrays.\nExperience with RTL and gate-level power analysis tools and methodologies.\nExposure to DFT concepts: scan insertion, ATPG, and DFT-friendly RTL coding.\nScripting skills (Python, Tcl, Perl) to automate design flows.\nWe offer a competitive base salary for this role, generally ranging from $180,000 to $245,000, plus a 10% annual bonus, meaningful equity, and comprehensive benefits. Final compensation will depend on experience, level, and location, with flexibility for the right candidate.\nWhy Join Efficient?\nBuild what's next. At Efficient, you'll tackle big challenges with room to take ownership and make an impact. We back you with competitive pay, equity, a 401(k) match, company-paid benefits, paid parental leave, and flexibility-plus opportunities to grow your skills and career as we scale.","description_format":"text","description_chars":5460,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":["Equity","Parental leave"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-14T23:26:56Z"}],"visa":[],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":0,"expected_fill_days":31,"reasons":["conf:2","velocity","win:early"],"computed_at":"2026-10-15T05:46:00Z"},"pay":{"stated_usd_annual":245000,"is_top_pay":true},"html_url":"https://alion.io/job/efficient-computer-senior-rtl-design-engineer","json_url":"https://alion.io/job/efficient-computer-senior-rtl-design-engineer.json","meta":{"generated_at":"2026-10-15T12:59:57Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":19986,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-16T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":2217001},"rest":"https://alion.io/mcp/rest/get_company?id=2217001"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fefficient-computer-senior-rtl-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fefficient-computer-senior-rtl-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fefficient-computer-senior-rtl-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/efficient-computer-senior-rtl-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fefficient-computer-senior-rtl-design-engineer"}]}