{"id":2495187,"url":"https://alion.io/job/elbit-systems-verification-team-leader","title":"Verification Team Leader","company":{"id":180,"name":"Elbit Systems","domain":"elbitsystems.com","url":"https://alion.io/company/elbit-systems","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"C","score":60,"open_postings":323,"ghost_share":0.669,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-15T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Holon, Israel"],"countries":["IL"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":119000,"max_usd":271000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":696},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-08-09T06:46:00Z","employer_posted_date":"2026-10-01","last_verified_at":"2026-10-15T12:10:44Z","board_verified":true,"closed_at":null,"days_open":67,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":66},"description":"At our Holon site, we are looking for a Verification Team Leader to lead a team of Verification Engineers within our advanced FPGA Systems Development Group.\nThis role combines technological leadership, team management, and hands-on technical work, with responsibility for defining the verification strategy, establishing verification methodologies, driving AI adoption within the verification environment, and leading the verification process throughout the entire development lifecycle.\nKey Responsibilities:\nLead a team of experienced Verification Engineers\nLead the development of UVM-based verification environments for complex FPGA systems\nDrive the end-to-end verification process, from requirements definition through signoff, at both Block-Level and System-Level\nWork closely with Design, Architecture, Algorithm, System Engineering, and Integration teams\nDefine and lead verification strategies, automation initiatives, and continuous improvement of verification methodologies\nIntroduce and implement AI-driven workflows and tools within the verification environment\nManage multiple projects simultaneously, prioritize tasks, and ensure successful execution against development objectives and schedules\nRequirements:\nB.Sc. in Electrical Engineering, Computer Science, or a related field\nAt least 8 years of experience in Verification Engineering\nStrong hands-on experience with SystemVerilog and UVM methodologies\nProven experience leading Verification teams\nExperience performing verification from Block-Level through System-Level\nBroad system-level perspective and strong understanding of FPGA development processes\nAbility to manage multiple projects and priorities in a dynamic environment\nExcellent leadership, communication, and presentation skills\nFast learner with the ability to adopt new technologies and methodologies\n*Only suitable candidates will be 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