Digital - ASIC Design Automation & Integration Engineer
Confirmed on the employer's own hiring board on Oct 26, 2026. First seen by Alion on May 13, 2026. Eliyan scores D on the Alion truth index.
Lint / CDC / Synthesis Quality · IP & Chip Integration · AI-Augmented Design Flows · CI/CD for RTL
On-Site Monday-Friday - Bay Area, CA / Vancouver, BC / Toronto, ON
Full-Time - Equity Participation - Comprehensive Benefits
ABOUT THE ROLE
Eliyan is the chiplet interconnect pioneer behind NuLink, the industry's most efficient chiplet-to-chiplet PHY technology. With Series C funding from leading hyperscalers and AI infrastructure providers, we are scaling our digital design organization to support multiple concurrent IP programs across advanced process nodes.
We are looking for an engineer who can own the intersection of design quality, automation, and design integration. In this role you will define and enforce signoff criteria for lint, CDC, and synthesis across all active programs, build the waiver management and tracking infrastructure, and develop AI-augmented tooling that turns thousands of tool violations into actionable, designer-ready reviews. You will report into the digital design team and work directly alongside RTL designers.
Design quality and automation are the core of this role. IP and chip-level integration ownership is scope you can grow into as you ramp - we're looking for someone who wants it.