{"id":2504603,"url":"https://alion.io/job/eliyan-digital-serdes-digital-design-lead","title":"Digital - SerDes Digital Design Lead","company":{"id":2652041,"name":"Eliyan","domain":"eliyan.com","url":"https://alion.io/company/eliyan","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":{"grade":"D","score":43,"open_postings":20,"ghost_share":0.95,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-19T05:45:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":[],"countries":[],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":151000,"max_usd":286000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":576},"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false}],"status":"live","first_seen_at":"2026-02-20T20:01:58Z","employer_posted_date":"2026-02-20","last_verified_at":"2026-10-19T22:26:59Z","board_verified":true,"closed_at":null,"days_open":241,"trust":{"level":"ghost","repost_count":0,"flags":["stale","company_stale"],"days_open":240},"description":"Join the leading chiplet startup! As the SerDes Digital Design Lead at Eliyan, you will drive the architecture and implementation of next-generation high-speed serial link IPs targeting 224G and 448G data rates for chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility. You will lead the digital design of SerDes transmitter and receiver datapaths, clock and data recovery (CDR) digital logic, equalization engines, and PHY-level controller logic for cutting-edge interconnect products. You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits.\nKey Responsibilities:\nLead the micro-architecture definition and RTL implementation of high-speed SerDes digital blocks targeting 224G PAM4 and 448G signaling, including DSP-based equalization (FFE, DFE, CTLE digital controls), CDR loop logic, and adaptation engines\nDesign and optimize PHY-level digital logic including TX driver control, RX datapath, PCS sublayers, lane alignment, deskew, and gear-boxing/rate-matching logic\nArchitect and implement forward error correction (FEC) encoder/decoder blocks including RS-FEC (KP4/KP8), interleaving, and low-latency FEC architectures optimized for 224G/448G link budgets\nDrive RTL design quality through lint, CDC/RDC analysis, synthesis optimization, and close collaboration with physical design and timing closure teams on advanced FinFET/GAA process nodes\nCollaborate closely with analog/mixed-signal designers on SerDes AFE integration, digital-to-analog interface specification, calibration sequencing, and AMS co-simulation bring-up\nOwn design deliverables and milestones from RTL development through tapeout signoff; coordinate with verification, DFT, and backend teams to meet aggressive schedules\nDefine and implement auto-negotiation, link training, and PHY initialization state machines compliant with IEEE 802.3\nDevelop power-efficient digital architectures with emphasis on clock gating, voltage scaling, and low-power design techniques for data center and AI/ML interconnect applications\nParticipate in standards bodies and stay current with emerging 224G/448G specifications, OIF CEI, and next-generation interconnect standards\nDesign firmware-accessible register interfaces, configuration/calibration logic, and DPI-based firmware co-simulation hooks for PHY bring-up and debug\nSupport post-silicon characterization and debug activities; correlate silicon measurements with pre-silicon simulation results to drive design improvements\nQualifications:\nMasters or Ph.D in Electrical Engineering, Computer Engineering, or related fields\n12+ years of experience in digital design of high-speed SerDes, PHY, or transceiver IPs with proven tapeout experience at 112G PAM4 or higher data rates\nStrong RTL design skills in SystemVerilog with deep understanding of synthesis, timing closure, CDC/RDC, and design-for-test (DFT) methodologies\nExpert-level knowledge of SerDes DSP architectures including FFE, DFE, MLSE, CTLE digital controls, CDR loop dynamics, and adaptation/calibration algorithms for PAM4 signaling\nStrong working knowledge of IEEE 802.3 (100G/200G/400G/800G/ 1.6T), OIF CEI specifications, FEC architectures (RS-FEC KP4/KP8), and/or die-to-die standards such as UCIe\nHands-on experience with high-speed digital design on advanced process nodes (5nm, 3nm, or below) with understanding of FinFET/GAA device implications on circuit performance and power\nExperience working at the digital-analog boundary including specification of DAC/ADC interfaces, calibration state machines, and integration with mixed-signal simulation environments\nDemonstrated technical leadership with ability to mentor engineers, drive architectural decisions, and deliver silicon on aggressive schedules in startup or high-growth environments\nExperience with optical/electrical interconnects (VCSEL, EML), chiplet D2D interfaces, DRAM PHYs, or HBM memory interfaces a plus","description_format":"text","description_chars":4093,"description_truncated":false,"requirements":{"experience_years_min":12,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","RF & Wireless Hardware"],"lifecycle":[{"event":"open","at":"2026-10-14T07:11:13Z"}],"visa":[],"liveness":{"score":4,"band":"cold","label":"Long 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