{"id":2504649,"url":"https://alion.io/job/eliyan-digital-staff-digital-design-engineer-phy","title":"Digital - Staff Digital Design Engineer - PHY","company":{"id":2652041,"name":"Eliyan","domain":"eliyan.com","url":"https://alion.io/company/eliyan","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Vancouver, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":103000,"max_usd":172000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":15},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Genus","optional":false},{"name":"HPC","optional":false},{"name":"Synopsys Fusion Compiler","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"TCL Scripting","optional":true}],"status":"live","first_seen_at":"2025-12-23T17:37:40Z","employer_posted_date":"2025-12-23","last_verified_at":"2026-10-15T01:58:23Z","board_verified":true,"closed_at":null,"days_open":295,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":295},"description":"Join the leading chiplet startup! As an Eliyan Staff Digital Design Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow's chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility. In this role you will lead the frontend design of our D2D PHY - the core tech behind NuLink, our chiplet interconnect platform. You'll own the digital PHY from microarchitecture through synthesis, working closely with our architecture, analog, verification, and physical design teams. This is a hands-on technical leadership role. You'll define PHY architecture, write RTL, optimize for synthesis, create timing constraints, develop firmware sequences, and ensure clean integration across the stack. Your work directly enables next-gen chiplet-based AI and HPC systems. We offer a fun work environment with excellent benefits. ONSITE M-F.\nKey Responsibilities:\nArchitecture & RTL Design\nOwn D2D PHY digital design from microarchitecture definition through synthesis and PD handoff\nDesign data path and clocking architecture for UCIe-compliant advanced package PHY\nWrite RTL for link training, calibration engines, rate adaptation, CDC, FIFO alignment, and lane deskew\nCreate microarchitecture specs with power analysis, latency metrics, and performance characterization\nMake architectural trade-offs balancing performance, power, area, and timing \nSynthesis & Optimization\nDrive synthesis optimization: area, timing, power, QoR\nCreate comprehensive SDC constraints for multi-clock domains, false paths, multi-cycle paths, CDC\nGenerate UPF power specifications with voltage domains, isolation, and retention\nEstablish LINT/CDC flows with rulesets and waiver management\nDeliver synthesis-ready netlists with handoff documentation for physical design\n Technical Leadership & Collaboration\nCoordinate with analog PHY team on digital control for TX/RX, PLL, calibration\nPartner with verification team on testbench requirements, coverage goals, and protocol compliance\nCollaborate with physical design on placement guidelines, clock tree requirements, routing constraints\nWork with firmware team on register interfaces, link training sequences, runtime control\nMentor 2-3 digital designers on frontend design and synthesis optimization\nDrive design reviews and technical decisions across teams\nRequired Qualifications:\n8+ years digital frontend design with 4+ years in PHY or high-speed interfaces\n3+ successful tapeouts as design lead in advanced nodes (7nm or below)\nDeep expertise in D2D PHY, DDR PHY, or SerDes digital design\nExpert SystemVerilog RTL design with strong synthesis optimization skills\nStrong understanding of UCIe or other high-speed interfaces like DDR/Serdes\nAdvanced CDC design, link training protocols, elastic buffer architectures\nHands-on with synthesis tools (Synopsys DC/Fusion Compiler or Cadence Genus)\nExperience with SDC constraints, UPF, STA methodology\nProven ability to lead frontend design and coordinate across teams \nPreferred Qualifications:\n12+ years with demonstrated technical leadership\nUCIe PHY design or certification experience\nDDR4/DDR5/LPDDR PHY or DFI interface experience\nSerDes digital control (TX/RX equalization, CDR), PCIe PHY, or CXL PHY experience\nAdvanced packaging knowledge: 2.5D, 3D, organic substrate\nFirmware development for PHY control or low-level driver implementation\nPython/Perl/Tcl scripting for design automation\nPublications or patents in PHY design","description_format":"text","description_chars":3486,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs 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