{"id":769026,"url":"https://alion.io/job/enchargeai-senior-pd-engineer-synthesis-sta","title":"Senior PD Engineer: Synthesis & STA","company":{"id":673158,"name":"EnCharge AI","domain":"enchargeai.com","url":"https://alion.io/company/enchargeai","size_band":"51-200","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"C","score":60,"open_postings":27,"ghost_share":0.667,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-11-04T06:34:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"remote","remote_scope":"stated_countries","remote_scope_basis":"board_field","remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":["IN"],"hiring_countries_total":1,"salary":null,"salary_estimate":{"min_usd":26000,"max_usd":68000,"period":"year","method":"role_seniority_country_cell","sample_n":18},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Genus","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"Formal Verification","optional":true}],"status":"live","first_seen_at":"2026-08-06T16:59:52Z","employer_posted_date":"2026-08-06","last_verified_at":"2026-11-04T07:35:55Z","board_verified":true,"closed_at":null,"days_open":89,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":89},"description":"Job Title: Senior PD engineer : Synthesis & STA\nLocation: Bangalore INDIA Hybrid / Remote\nRole Overview\nWe are seeking a highly skilled VLSI Synthesis & STA Specialist to take end-to-end ownership of logic synthesis and quality signoff for key blocks and sub-chips.\nIn this role, you will act as a critical bridge between the front-end design and back-end physical implementation teams.\nYou will not only drive synthesis execution to meet aggressive target frequencies but also act as an advisor to the RTL team, providing structural feedback to optimize the netlist.\nThis role offers a distinct growth trajectory, with the expectation to expand into adjacent physical design territories, including Place and Route (PNR) and comprehensive timing convergence.\nKey Responsibilities\nSynthesis Ownership: Drive and own the complete logic synthesis process for all designated blocks and sub-chips, ensuring optimal area, power, and performance metrics.\nQuality Signoff: Define, execute, and monitor rigorous sanity checks to achieve a high-quality, pristine Synthesis Signoff.\nRTL Collaboration: Work closely with RTL design engineers to ensure the delivery of a clean, fully linted netlist prior to handoff.\n Frequency & LOL Optimization: Deep dive into timing paths to ensure Levels of Logic (LOL) are strictly controlled and aligned with high-frequency target requirements.\nMicro-architecture Guidance: Go beyond reporting LOL violations; provide actionable RTL coding guidelines, structural recommendations, and micro-architecture inputs to help designers transform their code into a superior, synthesis-friendly netlist.\n Role Expansion: Progressively take on responsibilities in physical implementation adjacencies, actively participating in PNR execution, Static Timing Analysis (STA), and full-chip timing convergence.\nRequired Skills & Qualifications\nExperience: 5 to 8 years of proven experience in ASIC/SoC Logic Synthesis and Static Timing Analysis.\nEDA Tools Expertise: Hands-on experience with industry-standard synthesis tools, with a strong preference for Cadence Genus. Proficiency with STA signoff tools (e.g., Tempus, PrimeTime) is also required.\n Timing & STA: Strong foundational knowledge of STA, timing constraints (SDC), delay calculation, and multi-mode multi-corner (MMMC) analysis.\nRTL & Logic Fundamentals: Deep understanding of Verilog/SystemVerilog, digital logic design, and RTL linting/CDC tools.\nNetlist Optimization: Proven ability to analyze datapath architectures, identify logic bottlenecks, and recommend specific RTL changes to reduce logic depth.\nScripting/Automation: Proficiency in Tcl, Python, or Perl for developing and maintaining synthesis flow automation and customized reporting scripts.\nCross-Functional Communication: Excellent analytical and communication skills to effectively negotiate solutions between RTL and Physical Design teams.\nPreferred Qualifications\nPrior exposure to Place and Route (PNR) flows (e.g., Innovus, ICC2) and a solid understanding of how synthesis decisions impact physical placement and routing congestion.\nExperience with Formal Verification / Logic Equivalence Checking (LEC/Formality).\nKnowledge of advanced technology nodes (e.g., 5nm, 3nm) and their specific synthesis/timing challenges.","description_format":"text","description_chars":3264,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"India","iso":"IN","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-09-11T20:57:02Z"}],"visa":[],"liveness":{"score":10,"band":"cold","label":"Long shot","p_open":1,"p_active":0.342,"p_room":0.28,"age_days":89,"expected_fill_days":35,"reasons":["conf:3","stale_co","win:tail","crowd:"],"computed_at":"2026-11-04T06:34:25Z"},"pay":null,"html_url":"https://alion.io/job/enchargeai-senior-pd-engineer-synthesis-sta","json_url":"https://alion.io/job/enchargeai-senior-pd-engineer-synthesis-sta.json","meta":{"generated_at":"2026-11-04T08:22:10Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":13059,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-05T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":673158},"rest":"https://alion.io/mcp/rest/get_company?id=673158"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fenchargeai-senior-pd-engineer-synthesis-sta"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fenchargeai-senior-pd-engineer-synthesis-sta"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fenchargeai-senior-pd-engineer-synthesis-sta"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/enchargeai-senior-pd-engineer-synthesis-sta\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fenchargeai-senior-pd-engineer-synthesis-sta"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":769026}},{"tool":"search_jobs","arguments":{"company":"enchargeai.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":769026},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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