{"id":1736374,"url":"https://alion.io/job/ericsson-asic-synthesis-ppa-engineer","title":"ASIC Synthesis & PPA Engineer","company":{"id":56456,"name":"Ericsson","domain":"ericsson.com","url":"https://alion.io/company/ericsson","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Eightfold","truth_index":{"grade":"B","score":75,"open_postings":69,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":27,"computed_at":"2026-10-06T05:45:30Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Stockholm, Sweden"],"countries":["SE"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":66000,"max_usd":153000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1439},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Python","optional":false}],"status":"live","first_seen_at":"2026-09-05T02:31:49Z","employer_posted_date":"2026-10-02","last_verified_at":"2026-10-06T23:55:53Z","board_verified":true,"closed_at":null,"days_open":31,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":31},"description":"Join our Team\nAbout this opportunity:\nDo you enjoy solving the hardest problems at the intersection of RTL, timing, power, area and physical implementation? This is an opportunity to take ownership and constraint development for high-performance, low power SoC designs.\nWe are hiring an experienced ASIC Synthesis & PPA Engineer. Your primary focus will be physical-aware synthesis, floorplan-driven netlist optimization, STA & QoR closure - while also actively identifying opportunities in RTL & microarchitecture level to improve the design PPA. You will work closely with RTL design, Integration, architecture, place-and-route, and DFT teams throughout the full design cycle.\nWhat you will do:\nExecute physical-aware and floorplan-driven synthesis flows to reduce post-layout timing and congestion risks.\nIdentify and resolve synthesis bottlenecks: critical path restructuring, datapath optimization, and register retiming. \nDrive QoR closure by tracking key metrics across design iterations and process corners while providing expert feedback on RTL coding guidelines and synthesizability.\nWork on PPA optimization and structured design space exploration.\nRun block-level and full-chip STA for timing analysis across PVT corners, support MMMC timing closure, and analyze clock domain crossing (CDC) checks.\nValidate UPF/CPF power intent implementation, including isolation cells, level shifters, and retention registers, for correctness and power impact.\nCollaborate with RTL, physical design, and silicon teams on early floorplan exploration, area optimization, pin assignment, and PPA trade-off analysis.\nApply approved AI-assisted tools for log analysis, QoR comparison, and root cause investigation, while independently validating all generated results with sound engineering judgement. \nThe skills you bring:\n8+ years of experience in physical synthesis or logic design implementation.\nExpert-level experience with Synopsys/Cadence EDA tools.\nStrong SDC constraints authoring and management skills, including clock definitions, generated clocks, I/O delays, and timing exceptions such as false paths and multicycle paths.\nExperience in low power design strategies.\nExperience in analyzing PPA results and providing actionable microarchitecture & RTL-level recommendations to improve the same.\nProficiency in TCL; Python scripting is a strong plus.\nMultiple tape-outs on 7nm or below \nWhy join Ericsson? At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.\nWhat happens once you apply?Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.\nPrimary country and city: Sweden (SE) || Stockholm\nReq ID: 790595","description_format":"text","description_chars":3426,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Mobile Networks","Telecom Infrastructure","Network Equipment"],"lifecycle":[{"event":"open","at":"2026-10-03T01:10:14Z"}],"visa":[],"liveness":{"score":28,"band":"fade","label":"Fading","p_open":1,"p_active":0.517,"p_room":0.55,"age_days":31,"expected_fill_days":27,"reasons":["conf:1","stale_co","velocity","win:tail","comp:brand"],"computed_at":"2026-10-06T05:45:30Z"},"pay":null,"html_url":"https://alion.io/job/ericsson-asic-synthesis-ppa-engineer","json_url":"https://alion.io/job/ericsson-asic-synthesis-ppa-engineer.json","meta":{"generated_at":"2026-10-07T00:20:17Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":505,"day_limit":5000,"remaining_today":4495,"minute_limit":60,"resets_at":"2026-10-08T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":56456},"rest":"https://alion.io/mcp/rest/get_company?id=56456"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fericsson-asic-synthesis-ppa-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fericsson-asic-synthesis-ppa-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fericsson-asic-synthesis-ppa-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/ericsson-asic-synthesis-ppa-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fericsson-asic-synthesis-ppa-engineer"}]}