{"id":1950856,"url":"https://alion.io/job/ericsson-experienced-engineer-asic-backend-synthesis","title":"Experienced Engineer - ASIC Backend Synthesis","company":{"id":56456,"name":"Ericsson","domain":"ericsson.com","url":"https://alion.io/company/ericsson","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Eightfold","truth_index":{"grade":"B","score":77,"open_postings":80,"ghost_share":0,"stale_share":0.938,"repost_share":0,"time_to_fill_p50_days":26,"computed_at":"2026-10-09T06:01:00Z"}},"role":"Backend","role_family":"Backend","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":18000,"max_usd":45000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":133},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Agile","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Fusion Compiler","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"Synopsys Design Compiler","optional":true}],"status":"live","first_seen_at":"2026-06-17T09:21:22Z","employer_posted_date":"2026-10-06","last_verified_at":"2026-10-09T22:06:15Z","board_verified":true,"closed_at":null,"days_open":114,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":112},"description":"Grow with us\nJoin Ericsson’s cutting-edge journey to shape the future of 5G networks! As an Physical Synthesis Engineer, you’ll work on pioneering digital ASIC designs vital to Ericsson’s mobile network infrastructure. Our team, responsible for the final critical stage of chip design before fabrication, thrives on Lean and Agile principles, promoting close collaboration, daily progress-sharing, and continuous improvement. If you’re passionate about advanced technology and ready to make a meaningful impact in telecom, this role is crafted just for you.\nAt Ericsson, we support your growth, offering opportunities to advance your skills while contributing to game-changing 5G/6G technologies. Here, you’ll find a supportive, innovative environment focused on quality, teamwork, and career development. Join us and help shape the future of telecom!\nWe are hiring a Physical Synthesis Engineer to own the synthesis flow and constraint development on high-performance, low-power SoC designs. Your primary focus will be physical-aware synthesis, floorplan-driven netlist optimization, and QoR closure - while also contributing to static timing analysis (STA) signoff as well. You will work closely with RTL design, place-and-route, and DFT teams throughout the full design cycle.\nWhat you will do:\nPhysical-Aware Synthesis (PAS)\nExecute physical-aware and floorplan-driven synthesis flows to minimize post-layout timing and congestion surprises. \nIntegrate synthesis with P&R tools for early physical feedback loops - congestion-aware optimization, placement-aware buffering, and pre-CTS timing. \nCollaborate with P&R engineers on DEF/floorplan hand-off; iterate on netlist quality to reduce downstream ECO effort. \nPerform flat and hierarchical synthesis for large designs; manage partitioning and interface timing budgets. \nPerform formal or equivalence check on the netlist at block or top level. \nQoR & Optimization\nTrack and report key QoR metrics - timing slack, area, cell count, power - across design iterations and process corners. \nIdentify and resolve synthesis bottlenecks: critical path restructuring, datapath optimization, and register retiming. \nProvide RTL coding guideline feedback to design teams to improve synthesizability and QoR from the source. \nManage technology library characterization inputs: Liberty (.lib), LEF, and UPF/CPF for multi-voltage designs. \nOwn synthesis QoR sign-off checklist and contribute to tape-out readiness reviews. \nStatic Timing Analysis\nRun block-level and full-chip STA using PrimeTime (PT) for timing analysis across PVT corners. \nSupport MMMC (Multi-Mode Multi-Corner) timing closure; analyze and triage timing violations with P&R and synthesis teams. \nReview and validate SDC constraints developed during synthesis against post-layout STA results. \nContribute to clock domain crossing (CDC) checks and timing exception audits during signoff. \nThe skill you bring:\n5+ years in physical synthesis or logic design implementation \nExpert-level use of Fusion Compiler \nStrong SDC constraint authoring and management skills \nExperience with physical-aware synthesis flows and P&R hand-off \nWorking knowledge of STA (PrimeTime) \nProficiency in Tcl; Python scripting a strong plus \nAt least one tape-out on 7nm or below\nNice to have:\nFamiliarity with low-power methodologies (UPF/CPF, multi-Vt, clock gating) \nUnderstanding of PTPX-based power analysis flows \nDFT synthesis experience (scan, BIST, boundary scan) \nFamiliarity with congestion-aware and timing-driven P&R closure \nEDA Tools & Environment\nDesign Compiler, Fusion Compiler, Synopsys PrimeTime, Formality, Tcl/Python.\n.\n“All academic credentials must be from recognized and accredited institutions and are further subject to verification.”\nWhat happens once you apply?Click Here to find all you need to know about what our typical hiring process looks like.We encourage you to consider applying to jobs where you might not meet all the criteria. We recognize that we all have transferrable skills, and we can support you with the skills that you need to develop.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.\nPrimary country and city: India (IN) ||\nJob details: Developer\nJob Stage: Job Stage 5\nPrimary Recruiter: Ashwini Manda\nHiring Manager: Govinda Raju","description_format":"text","description_chars":4671,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Mobile Networks","Telecom Infrastructure","Network Equipment"],"lifecycle":[{"event":"open","at":"2026-10-06T09:59:53Z"}],"visa":[],"liveness":{"score":8,"band":"cold","label":"Long shot","p_open":1,"p_active":0.299,"p_room":0.28,"age_days":113,"expected_fill_days":26,"reasons":["conf:0","stale_co","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-09T06:01:00Z"},"pay":null,"html_url":"https://alion.io/job/ericsson-experienced-engineer-asic-backend-synthesis","json_url":"https://alion.io/job/ericsson-experienced-engineer-asic-backend-synthesis.json","meta":{"generated_at":"2026-10-10T01:15:38Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":2152,"day_limit":5000,"remaining_today":2848,"minute_limit":60,"resets_at":"2026-10-11T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":56456},"rest":"https://alion.io/mcp/rest/get_company?id=56456"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fericsson-experienced-engineer-asic-backend-synthesis"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fericsson-experienced-engineer-asic-backend-synthesis"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fericsson-experienced-engineer-asic-backend-synthesis"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/ericsson-experienced-engineer-asic-backend-synthesis\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fericsson-experienced-engineer-asic-backend-synthesis"}]}