{"id":4042526,"url":"https://alion.io/job/ericsson-principal-cad-rtl-methodology-and-design-engineer","title":"Principal CAD RTL Methodology and Design Engineer","company":{"id":56456,"name":"Ericsson","domain":"ericsson.com","url":"https://alion.io/company/ericsson","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Eightfold","truth_index":{"grade":"B","score":83,"open_postings":118,"ghost_share":0.025,"stale_share":0.517,"repost_share":0.153,"time_to_fill_p50_days":35,"computed_at":"2026-11-15T07:52:55Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence JasperGold","optional":false},{"name":"Jenkins","optional":false},{"name":"Linux","optional":false},{"name":"Python","optional":false},{"name":"Synopsys SpyGlass","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-10-19T15:54:45Z","employer_posted_date":"2026-11-10","last_verified_at":"2026-11-15T08:22:52Z","board_verified":true,"closed_at":null,"days_open":27,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":27},"description":"Grow with us\nAbout this opportunity:\nPrincipal CAD RTL Methodology and Design Engineer\nAustin, Texas. This is not a remote work opportunity\nDefine how Ericsson writes and signs off RTL, from coding rules to lint, CDC and RDC sign off. Combine hands-on RTL design with methodology leadership, software engineering, and practical AI to raise design quality across ASIC and FPGA programs.\nWork on ASIC and FPGA programs for Ericsson’s 5G and 6G portfolio at advanced nodes, including Intel 18A and TSMC 3/2nm. Drive measurable gains in RTL quality, IP reuse, and time to a qualified netlist through vendor-agnostic static signoff, reusable RTL frameworks, and AI-assisted design.\nWe are seeking a hands-on technical leader to own our RTL design methodology and static signoff flows-not simply support existing tools. Roughly half your time is spent on RTL design, so methodology decisions stay grounded in real product work.\nYou will work across RTL design automation, verification methodology, and OneRun, our front-end flow orchestration platform, partnering with IP and SoC design leads, domain methodology leads, back-end teams, and EDA vendors across Austin, Stockholm, Lund, and India. Own technical direction and qualified methodology; partner with the Silicon CAD Technical Program Manager on integrated delivery and adoption. Project design leads retain RTL signoff approval.\nWhat you will do\nOwn RTL design methodology: Define coding guidelines, lint rule sets, waiver policy, and signoff criteria for IP, subsystem, and SoC teams. Govern changes with design leads and mentor engineers in RTL best practices.\nLead lint, CDC, and RDC signoff: Architect structural, formal, and hybrid CDC and RDC flows with progressive goals and hierarchical signoff using abstract models and clock/reset constraints. Keep signoff criteria independent of the tool.\nBuild vendor-agnostic flows: Deliver single-command static signoff in OneRun with standard project templates and Jenkins CI quality gates. Qualify rule mapping between vendor tools on clean and dirty RTL before production use.\nDrive RTL reuse and automation: Architect configurable RTL frameworks and standard interfaces for multi-program IP reuse. Set the strategy for our next-generation register generation tool, with generated RTL that is signoff-clean.\nApply AI to RTL engineering: Use and improve AI tools such as ChipAgents and Kiro for RTL development, documentation, code conversion, and lint and CDC triage. Evaluate against manual baselines; retain engineering review.\nStrengthen the FE-BE handoff: Define RTL quality, SDC, and UPF checks for netlist handoff with synthesis, DFT, and back-end teams. Roll out changes through representative pilots without disrupting active tapeout schedules.\nJoin our Team\nWhat you will bring\n10+ years in ASIC/SoC RTL design and front-end methodology, with evidence of production deployment and successful tapeout contributions.\nDeep hands-on expertise in SystemVerilog/Verilog RTL design and microarchitecture for complex IP and SoC blocks, including parameterized and low-power design with UPF.\nStrong experience with Synopsys VC SpyGlass and/or Cadence JasperGold for lint, CDC, and RDC, plus an understanding of synthesis, timing, and DFT dependencies. Specialist depth in one or more signoff domains is valued; expertise in every domain is not required.\nStrong Python and scripting skills, with experience building maintainable automation using Linux, version control, code review, CI, automated tests, and controlled releases.\nDemonstrated ability to set standards that design teams adopt, explain technical trade-offs, and lead through technical credibility across distributed teams.\nA bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field-or equivalent practical experience.\nOwn the engineering behind how RTL is written and signed off-not just a step within it. Shape methodology while staying hands-on in design, work directly with IP and SoC teams and EDA vendors, and turn new methodology and AI ideas into production capabilities. Your impact will be measured in cleaner RTL, faster integration, and signoff flows that designers trust across programs.\nWhat happens once you apply?\nClick Here to find all you need to know about what our typical hiring process looks like.\nEricsson uses a merit-based hiring approach that values people with different experiences, perspectives and skillsets. We truly believe this approach drives innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity employer, learn more.\nIf you need assistance or to request an accommodation due to a disability, please contact Ericsson at .\nDISCLAIMER: The above statements are intended to describe the general nature and level of work being performed by employees in this position. They are not an exhaustive list of all responsibilities, duties and skills required for this position, and you may be required to perform additional job tasks as assigned.\nPrimary country and city: USA || Austin, Texas\nJob details: Developer\nPrimary Recruiter: Jim Everett \nCompensation and Benefits at Ericsson\nAt Ericsson, we know that our people are the key to our success. We offer a competitive package to help with your individual needs and goals.\nYour Pay\nThe salary range for this position is dependent on various factors including, but not limited to, location, and the candidate’s combination of job-related knowledge, qualifications, skills, education, training, and experience.\nShort-Term Variable Compensation Plan: Your pay also includes the opportunity for an annual bonus. Actual bonus payouts are based on performance of the business against the unit’s objectives, individual performance, and the individual bonus target. Certain eligibility and pro-ration rules apply.\nYour Health\nEricsson offers excellent health benefits including the choice of three medical plan options and a dental plan option that allow an employee to select the level of coverage that suits their needs. Employees will receive company credits in an amount equal to the cost that Ericsson pays toward the cost of their medical and dental premiums for themselves and eligible covered dependents.\nYour Financial Security\nWe invest in both your short and long-term financial wellbeing. The Ericsson US 401(k) Plan offers an automatic 3% company contribution and Ericsson match $1 for every $1 you put into the 401(k) Plan on the first 3% of your eligible pay, plus 50 cents on every $1 on the next 2% of eligible pay. When you contribute at least 5% of eligible pay, you are receiving Ericsson’s full matching contributions of 4%. Matching and company automatic contributions stop when your total eligible pay for the year reaches the IRS limits. Employees will also receive company credits in an amount equal to the cost of basic life insurance and basic accidental death and dismemberment coverage, as well as short-term and long-term disability coverage. Employees also have the option to participate in Ericsson’s Stock Purchase Plan.\nYour Time\nYour work-life balance is important to us. New employees are provided a minimum of 15 days of accrued vacation, up to 3 personal days per year, 11 annual holidays, 8 hours of volunteer time, and 80 hours of sick time annually. Please note paid time off is pro-rated based on the employee’s start date. Furthermore, Ericsson provides up to 16 weeks of paid maternity leave and 6 weeks of parental or adoption leave at 100% of pay.\nAdditional Benefits\nEricsson offers many other company-paid benefits such as financial wellness programs, educational assistance, matching gifts, and recognition programs.","description_format":"text","description_chars":7851,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Life insurance","Wellness"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Mobile Networks","Telecom Infrastructure","Network Equipment"],"lifecycle":[{"event":"open","at":"2026-11-10T22:40:47Z"}],"visa":[{"country":"US","licensed_sponsor":true,"adverts_offering_sponsorship_24m":0,"sanctioned_now":false,"evidence":"H-1B filings in 12 months: 85 · green card filings: 3","filings_12m":85,"filings_prev_12m":178,"green_card_filings_12m":3,"median_offered_wage_usd":122159,"route":null,"cap_exempt":false,"checked_at":"2026-11-15T09:21:55+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":21}],"liveness":{"score":46,"band":"ok","label":"Likely open","p_open":1,"p_active":0.616,"p_room":0.75,"age_days":26,"expected_fill_days":35,"reasons":["seen:4","stale_co","velocity","win:late","comp:brand"],"computed_at":"2026-11-15T07:52:55Z"},"pay":null,"html_url":"https://alion.io/job/ericsson-principal-cad-rtl-methodology-and-design-engineer","json_url":"https://alion.io/job/ericsson-principal-cad-rtl-methodology-and-design-engineer.json","meta":{"generated_at":"2026-11-15T19:03:53Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":12405,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-16T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":56456},"rest":"https://alion.io/mcp/rest/get_company?id=56456"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fericsson-principal-cad-rtl-methodology-and-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"free","price":{"credits":0,"usd":0},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fericsson-principal-cad-rtl-methodology-and-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fericsson-principal-cad-rtl-methodology-and-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/ericsson-principal-cad-rtl-methodology-and-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fericsson-principal-cad-rtl-methodology-and-design-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":4042526}},{"tool":"search_jobs","arguments":{"company":"ericsson.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":4042526},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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