{"id":1886202,"url":"https://alion.io/job/ericsson-soc-hardware-architect","title":"SoC Hardware Architect","company":{"id":56456,"name":"Ericsson","domain":"ericsson.com","url":"https://alion.io/company/ericsson","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Eightfold","truth_index":{"grade":"B","score":75,"open_postings":69,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":27,"computed_at":"2026-10-06T05:45:30Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":147000,"max_usd":266000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":402},"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"LLM","optional":false},{"name":"Multimodal AI","optional":false},{"name":"Python","optional":false},{"name":"Quantization","optional":false},{"name":"Transformers","optional":false}],"status":"live","first_seen_at":"2026-04-12T08:04:48Z","employer_posted_date":"2026-09-08","last_verified_at":"2026-10-06T21:09:23Z","board_verified":true,"closed_at":null,"days_open":177,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":176},"description":"Grow with us\nSoC Hardware Architect\nThe Architect Who Closes the Gap. The Engineer Who Makes Silicon Inevitable.\nLocation: Austin, TX Team: Cross-functional leadership across Model Engineering, AI Infrastructure, and Silicon Architecture\nThe Problem Nobody Else Is Solving\nMost chip programs are full of brilliant people who never quite speak the same language.\nResearchers build ambitious AI models. Silicon teams build powerful hardware. Infrastructure teams wire it all together. And somewhere in the space between those three worlds - in the handoffs, the assumption gaps, the untranslated requirements - massive performance dies quietly on the floor.\nWe're not hiring someone to manage that problem. We're hiring the person who architects it out of existence.\nThe Role\nAs Principal SoC Hardware Architect, you will own the most consequential technical contract in the company: the binding agreement between what AI workloads demand, what software systems can express, and what custom silicon can physically deliver.\nThis is not a support role. This is not a liaison role. This is the highest-leverage engineering seat in the building - the person who looks at a next-generation LLM, a multimodal inference pipeline, or a signal processing workload and answers the question that determines whether a chip program succeeds or settles:\n\"Here's exactly what this workload needs from silicon - and here's the proof it will work before we ever tape out.\"\nYour decisions won't live in documents. They'll be etched into hardware. Your performance models will guide compute investments. Your architectural direction will shape memory hierarchies. Your cross-team alignment will determine whether the company builds capable hardware - or hardware nobody else can touch.\nWhat You'll Own\nAnalyze workload specific testcases tailored to real-world applications, using LLMs, multimodal systems, signal processing pipelines, inference engines - and translate them into the concrete hardware requirements that can be implemented.\nYou are the bridge that doesn't bend. You connect model engineering, AI infrastructure, and silicon architecture teams so that every major hardware investment is both architecturally sound and software-accessible. When workload ambition outpaces hardware capability, you find the path forward. When silicon innovation creates a performance unlock, you make sure the software stack can actually reach it.\nPerformance Modeling Ownership\nBefore a single gate is placed, your analytical, simulation, and cycle-approximate performance models are already shaping the architecture. You build and create the performance modeling environment that determine compute investments, memory hierarchy decisions, and feature prioritization - turning uncertainty into defensible, data-driven direction.\nReal Workload Validation\nYou profile real workloads on real and future platforms. You find the bottlenecks - in memory, compute, scheduling, and architecture - and you feed those findings directly into the next hardware and software cycle. No guesswork. No assumptions. Just ground truth.\nStrategic Technical Translation\nYou align people who think in different languages. Hardware architects, AI researchers, and infrastructure teams all operate with different mental models and different vocabularies. You translate across all of them - grounding every product decision in real workloads, measurable constraints, and practical execution paths.\nJoin our Team\nWhat You Bring\nAI/ML Systems Depth You understand modern AI architectures from the inside - inference systems, quantization strategies, deployment constraints, and how workload behavior actually manifests in silicon utilization. You don't just know what a Transformer does. You know what it costs.\nSilicon Architecture Fluency You've worked with processor, accelerator, or custom silicon architectures. Compute pipelines, memory hierarchies, on-chip interconnects, performance tradeoff analysis - this is native territory for you, not background reading.\nRequired Qualifications\n12+ years of industry experience across AI, systems, or silicon\nProven experience at the intersection of hardware and intelligent compute systems\nHardware/software co-design leadership across full product cycles\nDemonstrated performance modeling expertise - analytical, simulation, or cycle-approximate\nTrack record of influencing architectural and product decisions across multiple technical organizations\nExceptional written communication and technical specification ability\nStrong Python and C++ skills\nStrongly Preferred\nExperience with custom silicon, accelerators, or advanced hardware platforms\nPrior involvement in ISA definition, memory hierarchy design, or accelerator roadmap decisions\nWhy This Seat Matters\nCapable hardware gets built every year. Truly differentiated hardware - silicon that was purpose-built for the workloads that define an industry - is extraordinarily rare.\nThe difference between those two outcomes is usually one person: the architect who understood the workload deeply enough, the silicon clearly enough, and the software stack completely enough to hold the whole picture together.\nThat's the person we're building this role for.\nWhat happens once you apply?\nClick Here to find all you need to know about what our typical hiring process looks like.\nEricsson uses a merit-based hiring approach that values people with different experiences, perspectives and skillsets. We truly believe this approach drives innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity employer, learn more.\nIf you need assistance or to request an accommodation due to a disability, please contact Ericsson at .\nDISCLAIMER: The above statements are intended to describe the general nature and level of work being performed by employees in this position. They are not an exhaustive list of all responsibilities, duties and skills required for this position, and you may be required to perform additional job tasks as assigned.\nPrimary country and city: USA || Austin, Texas\nJob details: Developer\nPrimary Recruiter: Jim Everett \nCompensation and Benefits at Ericsson\nAt Ericsson, we know that our people are the key to our success. We offer a competitive package to help with your individual needs and goals.\nYour Pay\nThe salary range for this position is dependent on various factors including, but not limited to, location, and the candidate’s combination of job-related knowledge, qualifications, skills, education, training, and experience.\n\nLOCATION: Austin, Texas\nYour Health\nEricsson offers excellent health benefits including the choice of three medical plan options and a dental plan option that allow an employee to select the level of coverage that suits their needs. Employees will receive company credits in an amount equal to the cost that Ericsson pays toward the cost of their medical and dental premiums for themselves and eligible covered dependents.\nYour Financial Security\nWe invest in both your short and long-term financial wellbeing. The Ericsson US 401(k) Plan offers an automatic 3% company contribution and Ericsson match $1 for every $1 you put into the 401(k) Plan on the first 3% of your eligible pay, plus 50 cents on every $1 on the next 2% of eligible pay. When you contribute at least 5% of eligible pay, you are receiving Ericsson’s full matching contributions of 4%. Matching and company automatic contributions stop when your total eligible pay for the year reaches the IRS limits. Employees will also receive company credits in an amount equal to the cost of basic life insurance and basic accidental death and dismemberment coverage, as well as short-term and long-term disability coverage. Employees also have the option to participate in Ericsson’s Stock Purchase Plan.\nYour Time\nYour work-life balance is important to us. New employees are provided a minimum of 15 days of accrued vacation, up to 3 personal days per year, 11 annual holidays, 8 hours of volunteer time, and 80 hours of sick time annually. Please note paid time off is pro-rated based on the employee’s start date. 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