{"id":1289454,"url":"https://alion.io/job/eridu-asic-design-verification-lead","title":"ASIC Design Verification Lead","company":{"id":673094,"name":"Eridu","domain":"eridu.ai","url":"https://alion.io/company/eridu-2","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Rippling","truth_index":{"grade":"A","score":89,"open_postings":30,"ghost_share":0.1,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":159,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Saratoga, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":157000,"max_usd":299000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":576},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-02-18T19:09:08Z","employer_posted_date":"2026-02-18","last_verified_at":"2026-10-18T04:27:13Z","board_verified":true,"closed_at":null,"days_open":241,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":241},"description":"About Eridu\nEridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI. Today’s AI performance is frequently limited by communication bottlenecks. Eridu delivers multiple industry-first innovations across silicon, packaging, software, and systems to deliver a step function in AI networking - a network switch that is an order of magnitude improvement in bandwidth and radix versus today’s “state of the art” switches. This is the first silicon and system designed from the ground up for AI and the increase in radix and throughput unlocks greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs, improving reliability, simplifying operations and speeding AI data center deployments for faster time to revenue.\nThe company’s solutions and value proposition have been widely validated by leading hyperscalers.\nThe company has raised $200M to date including its most recent, oversubscribed Series A round led by Socratic Partners, John Doerr, Hudson River Trading, Capricorn Investment Group and Matter Venture Partners, with participation by SBVA, MediaTek, Bosch Ventures, TDK Ventures, Eclipse Ventures, and VentureTech Alliance, among others.\nEridu is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exists, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu has also assembled a world class IP, design and manufacturing ecosystem to execute on its vision, and counts TSMC as a key partner in our journey.\nVisit our website eridu.ai to learn more.\nPosition Overview\nWe are seeking a hands-on ASIC Design Verification Lead to own verification execution for complex, high-performance networking silicon. This role is a senior technical leadership position focused on driving verification strategy, infrastructure, and closure, while remaining deeply involved in day-to-day hands-on verification work.\nThis is not a people-manager-only role. The ideal candidate is a highly technical verification leader who has personally taken chips to tape-out, understands how verification breaks late in the cycle, and can drive functional correctness, coverage closure, and tape-out readiness in a fast-moving startup environment.\nResponsibilities\nVerification Strategy & Execution\nDefine and own block-, subsystem-, and chip-level verification strategies\nDevelop and maintain scalable verification environments using SystemVerilog and UVM\nDrive execution from test-plan definition through coverage and bug closure\nEnsure verification readiness as a gating requirement for tape-out\nHands-on Verification Development\nWrite and review high-quality testbenches, sequences, checkers, and scoreboards\nDevelop constrained-random, directed, and stress tests to validate complex corner cases\nActively debug functional failures across RTL, testbench, and simulation environments\nCoverage & Quality Ownership\nDefine functional, code, and assertion coverage goals\nAnalyze coverage results and identify verification gaps\nProvide clear, actionable feedback to RTL designers to improve design and test quality\nCross-Functional Debug & Collaboration\nPartner closely with RTL, architecture, physical design, and firmware teams\nDrive root-cause analysis of functional, performance, and integration issues\nSupport gate-level, timing-aware, and power-aware simulations as required\nPartner and support emulation and post silicon validation of the ASIC design\nFull-Chip & Pre-Silicon Validation\nLead full-chip verification planning, execution, and closure\nSupport emulation and acceleration environments where appropriate\nEnsure clean handoff to silicon bring-up teams with high confidence in design correctness\nExecution Discipline & Technical Leadership\nEstablish and enforce verification checklists and quality gates\nTrack verification progress and risk, proactively escalating issues\nLead by technical authority and hands-on contribution rather than coordination alone\nContinuously improve verification methodology, infrastructure, and best practices\nQualifications\nStrong hands-on experience in ASIC design verification\nProven track record of taking at least one complex ASIC to tape-out with direct verification ownership\nDeep expertise in SystemVerilog and UVM-based verification methodologies\nStrong understanding of ASIC design and verification flows, including simulation, coverage, and debug\nExperience with block-level through full-chip verification and integration\nAbility to drive execution in ambiguous, fast-paced startup environments\nExcellent communication skills and ability to collaborate across disciplines\nNice to Have\nNetworking ASIC verification experience (Ethernet-based systems preferred)\nExperience with gate-level, timing-aware, and low-power verification\nFamiliarity with high-speed interfaces and chip-to-chip interconnects\nExperience with emulation, acceleration, or FPGA-based validation\nPost-silicon debug experience and RTL-to-silicon correlation\nWhy Join Us?\nAt Eridu, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.\nThe starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.\nNotice to Recruiting Agencies\nEridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted to Eridu without prior written authorization from our recruiting team will be considered unsolicited and will become the property of Eridu. Eridu reserves the right to pursue and hire such candidates without any obligation to pay fees. Recruiting agencies are expressly instructed not to contact hiring managers, employees, or executives regarding open positions.","description_format":"text","description_chars":6564,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Network Equipment","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-09-26T07:29:28Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 4","filings_12m":4,"filings_prev_12m":2,"green_card_filings_12m":0,"median_offered_wage_usd":217500,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)"],"filings_for_role_12m":3}],"liveness":{"score":25,"band":"fade","label":"Fading","p_open":1,"p_active":0.708,"p_room":0.36,"age_days":240,"expected_fill_days":159,"reasons":["conf:3","velocity","win:tail","crowd:"],"computed_at":"2026-10-17T05:46:00Z"},"pay":null,"html_url":"https://alion.io/job/eridu-asic-design-verification-lead","json_url":"https://alion.io/job/eridu-asic-design-verification-lead.json","meta":{"generated_at":"2026-10-18T07:13:38Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":10839,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-19T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":673094},"rest":"https://alion.io/mcp/rest/get_company?id=673094"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Feridu-asic-design-verification-lead"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Feridu-asic-design-verification-lead"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Feridu-asic-design-verification-lead"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/eridu-asic-design-verification-lead\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Feridu-asic-design-verification-lead"}]}