{"id":658049,"url":"https://alion.io/job/eridu-software-engineer-high-speed-serdes","title":"Software Engineer – High-Speed SerDes","company":{"id":673094,"name":"Eridu","domain":"eridu.ai","url":"https://alion.io/company/eridu-2","size_band":"201-500","is_staffing_agency":false,"is_intermediary":true,"ats_vendor":"Rippling","truth_index":{"grade":"C","score":62,"open_postings":27,"ghost_share":0.63,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-09-23T05:45:00Z"}},"role":"Backend","role_family":"Backend","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"hiring_geo_confidence":"structured","locations":["Saratoga, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":170000,"max_usd":286000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":135},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"BERT","optional":false},{"name":"C++","optional":false},{"name":"Mojo","optional":false},{"name":"Python","optional":false}],"status":"live","first_seen_at":"2026-09-02T17:29:54Z","employer_posted_date":"2026-09-02","last_verified_at":"2026-09-23T17:04:30Z","board_verified":true,"closed_at":null,"days_open":21,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":20},"description":"About Eridu\nEridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI. Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability.\nThe company’s solutions and value proposition have been widely validated by leading hyperscalers.\nEridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu is working with best-in-class supply chain partners including silicon, packaging and systems.\nVisit our website eridu.ai to learn more.\nPosition Overview\nWe are seeking a highly experiencedSerDes software engineer to lead the development, bring-up, validation, and optimization of next-generation high-speed interfaces. The successful candidate will work with 224 Gb/s-per-lane EthernetSerDes, PCI Express, and UCIe chiplet interconnects in advanced networking and compute silicon.\nThis is a senior technical role requiring strong knowledge ofSerDes architecture, PHY initialization, link training, equalization, calibration, diagnostics, and system-level signal-integrity behavior. The engineer will work closely with analog and mixed-signal designers, ASIC architects, firmware teams, validation engineers, board designers, and system software developers.\nKey Responsibilities\nDevelop embedded software and firmware for configuring, initializing, calibrating, and monitoring high-speed SerDes PHYs.\nLead bring-up and optimization of 224G PAM4 SerDes used in Ethernet switch, networking, and accelerator products.\nDevelop software support for PCIe SerDes, including link initialization, training, equalization, lane management, error recovery, and diagnostics.\nDevelop software support for UCIe die-to-die interfaces, including PHY initialization, link training, lane repair, health monitoring, and failure analysis.\nImplement SerDes adaptation and calibration workflows, including:\nTransmitter amplitude, pre-cursor, and post-cursor tuning\nReceiver CTLE, VGA, DFE, and CDR configuration\nAdaptive equalization\nEye optimization and margining\nLane-to-lane skew management\nPolarity inversion and lane remapping\nBackground calibration and environmental compensation\n\nDevelop APIs, drivers, firmware interfaces, command-line tools, and diagnostic utilities for SerDes control.\nSupport Ethernet auto-negotiation and link training, including Clause 73 and Clause 72/136-related workflows where applicable.\nSupport PCIe LTSSM interaction, preset and coefficient negotiation, lane margining, retraining, and recovery.\nSupport UCIe link state management, PHY repair mechanisms, sideband interactions, and link reliability features.\nCreate automated characterization and production-test software for:\nPRBS generation and checking\nBER measurement\nEye scans and bathtub curves\nJitter and signal-margin analysis\nLoopback testing\nLane failure isolation\nChannel and package characterization\n\nAnalyze difficult link failures across silicon, package, board, connector, cable, and optical-module channels.\nCorrelate software-visible SerDes telemetry with oscilloscope, BERT, VNA, and simulation results.\nDevelop algorithms and policies for runtime SerDes health monitoring, telemetry, predictive failure detection, and fault recovery.\nOptimize SerDes performance across process, voltage, temperature, channel loss, and manufacturing variation.\nDefine software architecture and reusable abstractions that support multiple SerDes IP vendors and PHY generations.\nCreate technical specifications, programming guides, bring-up procedures, debug playbooks, and validation plans.\nMentor engineers and serve as the organization’s technical authority for SerDes software and system bring-up.\nRequired Qualifications\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.\nTypically 10 or more years of experience in SerDes firmware, PHY software, silicon bring-up, or high-speed interface validation.\nDeep understanding of high-speed serial-link fundamentals, including:\nPAM4 and NRZ signaling\nChannel loss, insertion loss, and return loss\nJitter, noise, crosstalk, and reflections\nClock and data recovery\nTransmitter feed-forward equalization\nCTLE and decision-feedback equalization\nBER, eye diagrams, and link margin\nForward error correction\n\nHands-on experience bringing up and debugging at least one advanced SerDes generation, preferably 112G or 224G PAM4.\nStrong experience with one or more of the following:\nEthernet SerDes and IEEE 802.3 link training\nPCIe Gen5, Gen6, or later-generation PHYs\nUCIe or another high-speed die-to-die interface\n\nStrong embedded programming skills in C and C++.\nExperience with Python or similar languages for automation, characterization, data analysis, and laboratory equipment control.\nExperience programming SerDes registers through MDIO, I²C, SPI, PCIe configuration space, memory-mapped registers, or vendor-specific interfaces.\nFamiliarity with embedded processors, microcontrollers, real-time firmware, interrupts, DMA, and hardware/software interfaces.\nExperience debugging pre-silicon models, emulation platforms, FPGA prototypes, and post-silicon devices.\nAbility to interpret schematics, package and board topology, channel models, IBIS-AMI results, and signal-integrity reports.\nExperience using laboratory equipment such as high-bandwidth oscilloscopes, BERTs, VNAs, protocol analyzers, and traffic generators.\nStrong root-cause analysis skills and the ability to debug complex issues spanning analog, digital, firmware, package, board, and system domains.\nPreferred Qualifications\nExperience with 224G-per-lane Ethernet PHYs and 800G, 1.6T, or higher-speed Ethernet systems.\nExperience with PCIe 6.x or PCIe 7.0, including PAM4 signaling, FLIT mode, FEC, and lane margining.\nExperience with UCIe PHY and adapter-layer bring-up in multi-die or chiplet-based systems.\nFamiliarity with long-reach, medium-reach, short-reach, very-short-reach, and die-to-die SerDes channels.\nExperience integrating third-party SerDes IP into an ASIC or SoC.\nExperience developing vendor-independent SerDes abstraction layers.\nKnowledge of CMIS, pluggable optics, retimers, active electrical cables, and linear-drive optics.\nFamiliarity with IEEE 802.3, PCI-SIG, and UCIe Consortium specifications.\nExperience with SerDes power optimization, fast link recovery, degradation detection, and field diagnostics.\nExperience developing production screening, yield-analysis, and manufacturing-test solutions.\nExperience working with advanced process nodes, 2.5D packaging, interposers, and chiplet-based architectures.\nTrack record of technical leadership, cross-functional execution, and mentoring.\nSuccess in This Role\nThe successful candidate will:\nBring up new SerDes interfaces quickly and methodically.\nEstablish stable links across challenging channels and operating conditions.\nConvert low-level SerDes capabilities into robust, maintainable software.\nProvide actionable diagnostics rather than opaque link-up or link-down status.\nReduce silicon bring-up and customer-debug time through automation and strong observability.\nBuild a reusable SerDes software architecture spanning Ethernet, PCIe, UCIe, and future high-speed interfaces.\nRole Scope\nThis position focuses onSerDes control software, embedded firmware, link management, diagnostics, characterization, and system-level optimization. It will work closely with-but does not replace-the analog/mixed-signalSerDescircuit-design function.\nWhy Join Us?\nAt Eridu, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.\nThe starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.\nNotice to Recruiting Agencies\nEridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted to Eridu without prior written authorization from our recruiting team will be considered unsolicited and will become the property of Eridu. Eridu reserves the right to pursue and hire such candidates without any obligation to pay fees. Recruiting agencies are expressly instructed not to contact hiring managers, employees, or executives regarding open positions.","description_format":"text","description_chars":9492,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Venture Capital","AI Infrastructure","Middleware Software"],"lifecycle":[{"event":"open","at":"2026-09-10T21:14:58Z"}],"liveness":{"score":54,"band":"ok","label":"Likely open","p_open":1,"p_active":0.602,"p_room":0.9,"age_days":20,"expected_fill_days":55,"reasons":["conf:5","stale_co","win:mid"],"computed_at":"2026-09-23T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/eridu-software-engineer-high-speed-serdes","json_url":"https://alion.io/job/eridu-software-engineer-high-speed-serdes.json","meta":{"generated_at":"2026-09-23T21:51:50Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers"}}