{"id":1002505,"url":"https://alion.io/job/eridu-substrate-layout-design-engineer","title":"Substrate Layout Design Engineer","company":{"id":673094,"name":"Eridu","domain":"eridu.ai","url":"https://alion.io/company/eridu-2","size_band":"201-500","is_staffing_agency":false,"is_intermediary":true,"ats_vendor":"Rippling","truth_index":{"grade":"C","score":62,"open_postings":27,"ghost_share":0.63,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-09-23T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"hiring_geo_confidence":"structured","locations":["Saratoga, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":121000,"max_usd":227000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":131},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Allegro","optional":false},{"name":"Mentor Xpedition","optional":false}],"status":"live","first_seen_at":"2026-09-15T22:41:16Z","employer_posted_date":"2026-09-15","last_verified_at":"2026-09-23T23:30:24Z","board_verified":true,"closed_at":null,"days_open":8,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":7},"description":"About Eridu\nEridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI. Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability.\nThe company’s solutions and value proposition have been widely validated by leading hyperscalers.\nEridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu is working with best-in-class supply chain partners including silicon, packaging and systems.\nVisit our website eridu.ai to learn more.\nPosition Overview\nWe are seeking an experienced Substrate Layout Design Engineer to own the physical layout and routing of large, high-density, multi-die organic packages and modules, and their associated high-speed interface boards. The role spans early routing feasibility through manufacturing release and includes high-speed serial interfaces, clock and control signals, and high-current power delivery within demanding electrical, mechanical, and fabrication constraints.\nThe successful candidate will work closely with package integration, ASIC, signal integrity, power integrity, mechanical, system, and manufacturing teams. This position requires strong hands-on layout capability, sound engineering judgment, and the ability to work directly with foundry, substrate, assembly, board-fabrication, and contract manufacturing partners.\nResponsibilities\nOwn end-to-end physical layout of advanced organic substrates using Siemens Xpedition, Cadence Allegro, including die and component placement, bump map and netlist alignment, escape and breakout routing, via planning, reference planes, and layer stack-up implementation.\nPerform early routing-feasibility studies using die floorplans, I/O placement, package and board interfaces, mechanical keep-out zones, manufacturing rules, and system level constraints; identify bottlenecks and recommend floorplan, bump map, or stack-up changes.\nImplement high speed serial and differential routing with controlled impedance, length and skew management, crosstalk control, via-transition optimization, and continuous return paths in accordance with SI requirements.\nRoute clock, control, management, and other low-speed interfaces while meeting topology, shielding, isolation, and reference plane requirements.\nDevelop robust power and ground distribution for high power devices and voltage regulation interfaces, including plane allocation, current density management, via arrays, and implementation of PI constraints.\nSupport package-to-board co-design and layout of high speed interface boards, including connector and component placement, signal breakout, power delivery, and mechanical alignment with the package or module.\nIntegrate fine pitch interconnect regions and embedded or integrated passive structures while observing electrical, mechanical, thermal, and supplier specific design rules.\nBuild and maintain layout constraints, technology files, libraries, design documentation, revision control, and ECO implementation throughout the design cycle.\nRun and resolve DRC, connectivity, DFM, and manufacturing rule checks; prepare complete release packages, drawings, reports, and design databases.\nLead layout reviews and work directly with foundries, substrate suppliers, OSATs, PCB fabricators, and contract manufacturers to resolve manufacturability issues and drive designs to release.\nMinimum Qualifications\n8+ years of hands-on experience in advanced IC package substrate layout, with substantial experience in high-performance organic substrates.\nDemonstrated experience with multi-die or chiplet-based packages, high I/O counts, fine-pitch bump escape, dense routing, and constrained layer stack-ups.\nStrong hands-on proficiency with Siemens Xpedition for package or substrate layout.\nExperience with package-to-board or complex PCB layout and an understanding of interactions among die floor plans, substrate layout, board interfaces, mechanical boundaries, and manufacturing rules.\nExperience completing design checks and releasing layout databases and manufacturing documentation to substrate or assembly suppliers.\nBachelor's degree in electrical, electronics, packaging, or a related engineering discipline, or equivalent relevant experience.\nPreferred Qualifications\nMaster's degree in electrical, electronics, packaging, or a related engineering discipline, or equivalent relevant experience.\nPractical experience implementing high-speed routing constraints for SerDes class interfaces, differential pairs, clocks, and other timing-sensitive signals.\nStrong technical communication, design review, problem-solving, and documentation skills, with the ability to coordinate across internal teams and external suppliers.\nPractical experience implementing high-current power and ground structures and working from SI and PI constraints and review feedback.\nExperience with large, high-I/O-count, or high layer count package and substrate layouts.\nIn addition to Siemens Xpedition, experience with Cadence Allegro Package Designer Plus.\nFamiliarity with advanced substrate materials, build up processes, microvias, embedded passives, fine-pitch local interconnect structures, and supplier design-rule development.\nExperience supporting a complex package or board design from feasibility and floorplanning through supplier review, manufacturing release, and build issue resolution.\nWhy Join Us?\nAt Eridu, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.\nThe starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.\nNotice to Recruiting Agencies\nEridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted to Eridu without prior written authorization from our recruiting team will be considered unsolicited and will become the property of Eridu. Eridu reserves the right to pursue and hire such candidates without any obligation to pay fees. Recruiting agencies are expressly instructed not to contact hiring managers, employees, or executives regarding open positions.","description_format":"text","description_chars":7417,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Venture Capital","AI Infrastructure","Middleware Software"],"lifecycle":[{"event":"open","at":"2026-09-17T13:29:39Z"}],"liveness":{"score":60,"band":"ok","label":"Likely open","p_open":1,"p_active":0.602,"p_room":1,"age_days":7,"expected_fill_days":46,"reasons":["conf:5","stale_co","win:early"],"computed_at":"2026-09-23T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/eridu-substrate-layout-design-engineer","json_url":"https://alion.io/job/eridu-substrate-layout-design-engineer.json","meta":{"generated_at":"2026-09-24T00:46:35Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers"}}